Hi, I am fairly new to FPGAs. I am trying to write the constraints for the PCI module on an Altera Stratix device. I am using QuartusII for all synthesis and P&R. The PCI spec says I need to ensure a setup time of 7ns for all pins. The PCI clock itself works at 33Mhz. I want to know the following:
1) Is it okay if I just constraint the PCI clk of my design to 50Mhz (30ns for the 33Mhz clock and another 10ns to ensures that the setup time is met)? I realise this will be an overkill on the internal logic but may save me some effort. 2) The other way I think to do this is to constraint the PCI clk to 33MHz and specify the external delay on all the PCI signals to 7 or 8ns. While setting PCI clk to 33Mhz I also ticked the option of including external delays in the frequency calculation. Is this the correct approach? OR do I need to setup the tco. Thanks in advance. Regards Tushit- posted
19 years ago