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conditional port generation in Verilog 2001

I'm really enjoying the 'generate' feature of Verilog-2001. However, I'm wondering if I can use it or something similar to add ports to the port list. I'm pretty sure I can't but I thought I'd ask. For example, if the number of ports is, say, four, I want to have four data buses in the port list, like so:

input [15:0] databus0, input [15:0] databus1, input [15:0] databus2, input [15:0] databus3, ...

Obviously for single-bit signals I can put them in a bus which has a width of four. But for buses, I either have to instantiate them separately, or have a 2-dimensional port, like [15:0] databus[0:3], which I don't think I can do.

-Kevin

Reply to
Kevin Neilson
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Kevin,

Unfortunately, I don't thing the generate statement can do conditional port generation. I also know from personal experience that

2-dimensional ports are not allowed. One nice thing you can take advantage of in this vein is to not declare every port when you instantiate something. So you declare all the possible ports you could need, but only instantiate the ones you want. For instance, if you have databus0, databus1, databus2, and databus3 as ports, you can still just instantiate the module as

mymodule i_mod ( .databus0(i_databus0), .databus1(i_databus1) );

Perhaps not a very convenient solution, but it might be better than nothing.

Mike

Reply to
mike.peattie

yes, like a dead log no way about it. a port is akin to a pin for a circuit and you simply cant make its presence to be dynamically determined.

Reply to
Neo

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