Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl.
Verilog =>
// string data type reg [8*4:1]a; reg [8*255:0]b;
VHDL =>
Is the above equivalent to variable a : string(1 to 8*4) variable b : string(1 to 8*255)
Just a thought..: variable b : string(0 to 8*255)
Unfortunatly not. String has a range that uses positive instead of integer, so must always be 1 to somthing. You cant use downto either.
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