Bogus Hold Violations with 2X clock on Xilinx ISE 7.1

I have a DCM that drives a 1X clock and 2X clock on BUFGs. In one case, the enable to a CLK2X register depends on a CLK1X based FF. Looking at the path delays, there is no problem with setup and hold, but the timing analyzer reports a hold violation that is essentially the actual path delay plus the CLK2X period. The required hold time is

Chris