altera latch synthesis

Hi all,

I have done some other investigations on the problem and I have a theory. As I already mentioned in the previous message the latch has been synthesized using a LUT of a LE. The SDF characterizes the lecomb by PORT and IOPATH statements; no TIMING CHECK is present. For simplicity consider EN signal statically at 1. If the D input has a transition just before the falling edge of CLK (< PORT(D) delay) an oscilation occurs. The explanation is the following: The D transition that occurs with CLK=1 throws a transition on Q (=LE's combout) after PORT(D)+IOPATH(D) delay. Neverthless the CLK causes the latch to hold Q value at CLK transition time after PORT(CLK)+IOPATH(CLK). This triggers the oscillation. Probably the situation is similar to setup time violation, but Quartus II models the latch via a LUT an surely there is no trace of this trouble in the static analysis.

Thanks, Andrea

"Andrea" ha scritto nel messaggio news:bj2k4f$5pf$ snipped-for-privacy@lacerta.tiscalinet.it...

example).

Do you really want a latch? As you've seen, the architecure doesn't support it directly, so it will get synthesised using luts. The static timing won't necesasrily be abel to handle it as it's an asynchronous latch, so you'll be on your own timing wise.

What was the question exactly?

Cheers, Martin

I don't want to modify a complex VHDL code, moreover the architecture pipeline needs latch to work properly without loosing performances. What do you suggest?

Andrea

"Mart>

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doesn't

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Why not? If there isn't a functional testbench, that is your first job.

Once you have a testbench, you can easily verify your changes.

You can pipeline just as fast with D flops. Use a PLL to double the clock if need be.

Take the bull by the horns and design out the latches.

-- Mike Treseler

Hi Mike, I think you are correct! This is the only one solution. Thank you,

Andrea