altera latch synthesis

Hi all,

I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE.
I have described a latch in my VHDL code with an enable signal, something
like this

library ieee;
use ieee.std_logic_1164.all;

entity my_lat is
    port (d : in std_logic;
          en : in std_logic;
          clk : in std_logic;
          q : out std_logic);
end my_lat;

architecture rtl of my_lat is
    signal next_q, q_local : std_logic;
begin
    next_q <= d when (en='1') else q_local;
    q_local <= next_q when (clk='1') else q_local;
    q <= q_local;
end rtl;

Quartus II synthesizes this code mapping the latch on a lut with the
following equation:

--A1L5 is q_local~1 at LC3_1_S1
--operation mode is normal
A1L5 = clk & (en & d # !en & A1L5) # !clk & A1L5;

The gate level backannotated simulation produces oscillation on q output.
Actually this what I see in a more complex design (this is only an example).
Looking the equations it seems to be all ok, even if SDF extracted doesn't
contain any TIMING CHECKS for combinatorial part of a LE, nevertheless the
equation describes a combinatorial loop.

(CELL
    (CELLTYPE "apex20ke_asynch_lcell" )
    (INSTANCE q_local_a16.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT dataa (3754:3754:3754) (3754:3754:3754) )
        (PORT datab (11093:11093:11093) (11093:11093:11093) )
        (PORT datac (3754:3754:3754) (3754:3754:3754) )
        (PORT datad (274:274:274) (274:274:274) )
        (IOPATH dataa combout (800:800:800) (800:800:800) )
        (IOPATH datab combout (783:783:783) (783:783:783) )
        (IOPATH datac combout (726:726:726) (726:726:726) )
        (IOPATH datad combout (335:335:335) (335:335:335) )
      )
    )
  )


Any suggestion?

Thanks in advance,
Andrea