Hold Time Violations in Virtex4

Hello,

Iam getting the following hold time violation in my design. Its happen on the address inputs to a instantiated ram16x1d primitive. Source and desitnation flipflops are in the same clock domain. There does not seem to be a clock skew and iam using local clock resources for this clock.

-------------------------------------------------------------------------------- Hold Violations: TS_lp_clkin_p = PERIOD TIMEGRP "lp_clkin_p" 5 ns HIGH 50%;

-------------------------------------------------------------------------------- Hold Violation: -0.089ns (requirement - (clock path skew + uncertainty - data path)) Source: lp_bus/rx/wr_addr_r[0] (FF) Destination: lp_bus/rx/l1.2.r.SLICEM_G (RAM) Requirement: 0.000ns Data Path Delay: -0.089ns (Levels of Logic = 1) Positive Clock Path Skew: 0.000ns Source Clock: lp_bus/rx/lp_clk rising at 0.000ns Destination Clock: lp_bus/rx/lp_clk rising at 5.000ns Clock Uncertainty: 0.000ns Timing Improvement Wizard Data Path: lp_bus/rx/wr_addr_r[0] to lp_bus/rx/l1.2.r.SLICEM_G Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.313 lp_bus/rx/wr_addr_r[0] net (fanout=10) e 0.100 lp_bus/rx/wr_addr_r(0) Tah (-Th) 0.502 lp_bus/rx/l1.2.r.SLICEM_G ---------------------------- --------------------------- Total -0.089ns (-0.189ns logic, 0.100ns route) (212.4% logic, -112.4% route)

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According to their latest data sheet Tah = -0.29 ns. But timing analyzer has it as Tah = 0.502 ( positive value)

I get same results on both ISE 7.1.04 and 8.1.03.

What am I missing? With a negative hold time, there should be no hold time violations. How do I update the timing models/data?

Thanks Brijesh

Reply to
Brijesh
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This particular path doesn't seem to be routed (note there is an "e" on the net delay line). You don't need to be concerned about hold time errors due to estimated delays.

HTH, Jim

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Reply to
Jim Wu

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