hi everybody , i have a few questions regarding setup and hold timing
what is the reason a hold time / setup time is needed....i tend to think its down at the transistor level but i cant exactly put my finger on it ...something to do with the prop delay?
would a level triggered , i.e. non master slave type flip flop have a setup time or just a hold time?.....since there is no intermediate now...
what happens if the hold/setup time is not met....does the output not change or does it become unpredictable?
I'd love answers to these questions.....a few links thrown in would be awesome!
Let me give you an analogy: If you want to fly somewhere, the airline tells you to be at their counter (say) one hour before departure time. That's the set-up time. They guarantee you that you will be let on the airplne if you appear on time. If you violate the set-up time, you take a chance. You may, or may not, get on the plane. Hold time is the ugly result of a design mistake inside the flip-flop, when the internal clock delay is longer than the internal data delay. For the past 40 years, IC designers have known how to avoid this problem inside the flip-flop. But it can pop up as a system problem, when clocks have too much delay.
What you call level-triggered flip-flop, I would call a latch, and it is half of a flip-flop. You need both the master and the latch, to prevent race conditions. Another analogy: A flip-flop behaves like the rotating hotel door. People (data) can get through, but the wind cannot blow through... Read some good text books! Peter Alfke
i dont understand....how is the internal clock delay greater than the data delay??
another thing....consider a simple gate ...what is the minimum time for which an input has to be held at the gate for its corresponding output to show ?....if there were a spike low-high-low of say 3 ns at the input , and gate Tpd is say 7 ns , would output register ?....and if it doesnt , doesnt the gate too then have some sort of a hold time requirement? and isnt this then where hold time originates?
You can imagine the setup and hold problem as a sampling settling issue. Imagine you are sitting on a table and someone far away is showing you red/blue flags. Every so often you have to lift your head see what color the flag is. If you catch the flag in transition you can't actually tell. Actually it's a window of time during which the sampling will be problematic. In the past it used to be that the starting time of the window was always before the clock and the end time was always after the clock so setup/hold times. These days with negative hold times, it's not that clear cut. The main thing is that you have to sample a signal when it is stable. If it is changing when you're looking at it, your result will not be consistent. With a latch, the same problem exists and the data has to be stable during a certain window so setup/hold parameters still exist. If this requirement is not met, the output is not predictable. It could get arbitrarily one or the other value or it could stay at an indeterminate electrival level for an arbitrarily long time (it could be metastable). For a synchronous digital circuit, violating the setup/hold times mean that your results will not be predictable.
When I first started out in digital design, an old-time engineer told me a few basic rules. The first was this:
"There is no such thing as digital."
In the realizable devices that engineers actually work with, there are only analog circuits approximating digital behavior.
The component wires and transistors creating a flop, a gate, any digital circuit, all have finite capacitances and resistances. The power supply can only deliver a finite current. Thus, any logic circuit node, to go from a logical 0 to a logical 1, will have a finite slew rate passing through the voltages in between those that define the logic levels. A flop is designed so that the output should only change during a window of time near the clock edge. Get there too late, and you can't slew the output all the way before the window in time ends. Change the input too soon and the output capacitor(s) may only get charged up part way to the new logic level. Either way, end up too close to the threshold, and your flop is no longer approximating a digital circuit. The people writing the data sheet call this a set-up or a hold-time violation (which saves them from having to fully document every gate and flop as an actual analog circuit).
Why can't one avoid this problem by defining any voltage as either a logical 1 or logical 0 so that there is no "in-between"? Old-timer electrical engineering rule #2:
"There is no such thing as ground."
Given any noise, as well as circuit variation, etc., a signal near the threshold is statistically undefined. Logic circuits need some margin to be reliable.
You still have both a setup and a hold time, since the gap in between is what defines a window in time relative to the clock signal. Whether one of either the setup time or the hold time is negative depends on the relative delays of the clock and the input.
You have an analog circuit. What happens next depends on the exact logic family and circuit design, ground noise, thermal noise, crosstalk, capacitive coupling, both positive and negative feedback paths, etc. etc.
This, of course, is just a brief sketch of the subject. Lot's of IEEE papers on the subject were published from the 70's onward.
IMHO. YMMV.
--
Ron Nicholson rhn AT nicholson DOT com http://www.nicholson.com/rhn/
Applications Engineering - Leopard Logic, Inc.
#include // only my own opinions, etc.
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