Hold violation and PLL

Dec 04, 2003 2 Replies
A

Hi, I have a problem on quartus II 3.0 software. I am using enhanced PLL and a set of input registers with FAST INPUT REG = on constraint. Thus i get about 1 ns delay of pad to IOB flop on datapath. However delay of clock from PLL to IOB flops is higher around 3 ns. Thus i get a hold violation of 2 ns. Anyone has any suggestions as to how i can eliminate this hold violation.



Shardendu


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M

Hi,

I think Quartus software, is for Altera FPGAs... I haven't used Altera FPGAs.

But in general i can give some options.

  1. Try to pack the First Flip Flop in to IOBs.. This option is available in Xilinx. I don't know about Altera.
  2. Make the data path pad property to SLOW
  3. Adjust the phase shift of PLL.. ie., delay it to caputre data in next clock cycle
  4. Else put some additonal dealy in the data path

Regards, Muthu

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M

What happens if you remove the constraint?

-- Mike Treseler

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