clock division using DCM, how?

Hello to all of you,

currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site (

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) is correct. So I assume the error is related to timing problems of some kind. I'm relatively new to the whole FPGA stuff and have to learn everything myself, and timing and constraints is so complicated that I often don't know where to start. If you take a closer look at the VHDL code you can see that in the vgacontroller entity a signal xclk is generated, this is just a 25MHz signal, which is then used for a whole lot of synchronization.

I have read about the clock nets available on FPGA and found something at

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about DCM. I suppose there's a better way to doing things than mine, I just don't really know how.

As a conclusion: how do I implement a clock on the "time net" with a frequency which is one fourth (25 MHz) of the hardware provided frequency (100 MHz)

Kind regards, Jef Patat

Reply to
tkanmijnischelen
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Dear Jef,

From what i understand, you are manually dividing the clock by 4. there is nothing wrong with this. Xilinx tool automatically identifies the clock signals, and tries assigning them a dedicated clock line. you can see it in the report of XST. What you need to do is to tell Xilinx tool that the clock generated by division is 25 MHz. Constraints! Otherwise, it would have no idea how to do the placement. However, the use of DCM is not mandatory is you want to only divide the clock by 4. But if you have too much, really too much combinational logic, then even the slow clock as 25 MHz will not meet timing.

hope this helps.

If you can give more details...

best regards, Vladislav

Reply to
Vladislav Muravin

Hello to all of you,

currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site (

formatting link
) is correct. So I assume the error is related to timing problems of some kind. I'm relatively new to the whole FPGA stuff and have to learn everything myself, and timing and constraints is so complicated that I often don't know where to start. If you take a closer look at the VHDL code you can see that in the vgacontroller entity a signal xclk is generated, this is just a 25MHz signal, which is then used for a whole lot of synchronization.

I have read about the clock nets available on FPGA and found something at

formatting link
about DCM. I suppose there's a better way to doing things than mine, I just don't really know how.

As a conclusion: how do I implement a clock on the "time net" with a frequency which is one fourth (25 MHz) of the hardware provided frequency (100 MHz)

Kind regards, Jef Patat

Reply to
Jef Patat

identifies the

Howdy Vladislav,

His XST report confirms that the tools do not automaticly put manually derived clocks on global clock nets.

by

placement.

the

I haven't studied his design enough to know how much it would benefit him, but in general, if you want to seemlessly transfer data between the domains, it is best to generate the main and divided clock from the same DCM so that they are phase aligned - and even then, depending on how concerned with jitter you are, you may want to do the transfer using a rising-falling edge combination.

even the

Agreed, although in a Virtex-2Pro, that would take a huge number of levels of logic at that speed (to make a WAG: 20 or 30 levels).

Have fun,

Marc

Reply to
Marc Randolph

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