Dear All: I have tried the reset circuit for external feedback DCM on XAPP462 Figure 20. Is it ok to use feedback clock input as the shift register to generate DCM reset? Modelsim's wave tell me that DCM will not output clock when it is at reset. A miss for XAPP462 Figure 20? Or I made the misunderstanding.
This is indeed a mistake in the diagram in Figure 20. The clock feeding the SRL16 should feed from the input clock (connected to CLKIN) and not from the feedback clock (connected to CLKFB).
I will make sure that this is updated when we update XAPP462.
--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs
--------------------------------- Spartan-3: Make it Your ASIC
reset? Modelsim's wave tell me that DCM will not output clock when it is at reset.
Dear XILINX: Thanks for the immediate help. I am happy to be a XILNX FPGA designer. Regards, seyior
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