DCM with instable clock

What sort of frequency range are you interested in?

This isn't "phase" as measured in degrees, but have you considered an external delay line? If you pick the delays for the fastest frequency the logic should still work when the clock slows down. But it might not give you the output you want.

Have you looked at clock generator chips? Some of them have multiple outputs at different speeds. You might get lucky and find something that fits you needs.

In the old days, the do-it-yourself clock generator was a PAL clocked at twice the highest speed you needed. (Or a '374 and a few gates.)

Thank you, Murray

It's my fault that I didn't make a clear description.

My whole project is based on a virtex-4 SX55 FPGA, only one clock_input, frequency up to 300MHz, and may chang to any frequency slower, but not under my control. So, in FPGA, I have to use some logic to generate some slower clock in the FPGA to feed internal logic, which have precisely phase relationship.

As the clock may change frequency while not even notified, how can I use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with given phase relationship without DCM? Can I use the LOCKED signal to reset DCM? Is it reliable?

Thanks!

Thank you, Murray

It's my fault that I didn't make a clear description.

My whole project is based on a virtex-4 SX55 FPGA, only one clock_input, frequency up to 300MHz, and may chang to any frequency slower, but not under my control. So, in FPGA, I have to use some logic to generate some slower clock in the FPGA to feed internal logic, which have precisely phase relationship.

As the clock may change frequency while not even notified, how can I use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with given phase relationship without DCM? Can I use the LOCKED signal to reset DCM? Is it reliable?

Thanks!

So you have an incoming clock that can be any frequency up to 300 MHz, and may also stop completely. Can you run your logic off another, stable oscillator? A DCM is not the only way to reduce the clock rate: You can use a simple binary counter for that.

Your question is incomplete. Therefore it is tough to suggest solutions. Peter Alfke, Xilinx Applications

-69.sjc.megapath.net (Hal

=D6 -

Hi, Peter

First, I don't have any other oscillators.

Second, as I know, it is tough to achieve phase relationship using binary counters. Phase relationship can change dramticly while frequency changs.Do you have any suggestions?

Third,can I use LOCKED signal to reset DCM? Is it reliable?

Thanks

-1-69.sjc.megapath.net (Hal

=D7=D6 -

If you want meaningful suggestions, you must tell us more about your design and its constraints. When you say that you have no continuously running oscillator: You can buy one for about $1.00. Peter Alfke

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I just have one question Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure?

Thanks

Not necessarily. At least in a Virtex II DCM, the LOCKED signal is not valid if the input clock stops. There is another signal in the STATUS outputs that indicates a loss of input clock, so you have to AND this with LOCKED to have an indicator of when your DCM is "working". Other FPGAs' DCMs or PLLs probably work differently than this, so you need to study the user guide to find out.

Barry

Not 'sure', as already mentioned, the status register has flags which you also need to check:

The most useful is "CLKIN" stopped bit DO(1). There are also other status bits you may wish to look at ("CLKFB" stopped) to decide if you should reset the DCM, or not.

Since the DCM is a synchronous state machine, if the clock input stops, the LOCKED signal will not transition, but the 'stopped' flag will.

Austin

So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or I can reset DCM inside FPGA using another clock_input. Only these 2 solutions?

Maybe I will do it in my next design, I cannot use DCM these time.

Anyway, thanks, all of you.

Yes,

Next time, be sure you have a local oscillator--your life will be far easier.

Aust>