Help with clock division question.

I've been messing around with a communications board lately which can have T1 or E1 interfaces. I'd like to change one into the other. Naturally I'll need to change the framing IC's (and a few other things not related to timing), but I think for it to run correctly, I need to also change the clock driving them.

Stuff I know:

The T1 framer uses a 1.544mhz master clock The E1 framer uses a 2.048mhz master clock The main clock for the whole board is 50.000mhz. There is only one clock crystal on the board, so everything must be derived from this crystal I would think. There are no PLL chips on the board that I can immediately identify There ARE flip-flops on the board, but I don't see how a flip flop would be used to generate either of these clock frequencies from a clock of exactly

50.000mhz, since 50.000 does not divide down evenly into either 1.544 or 2.048 There ARE quite a few FPGA's on the board, and the identity of the board (whether it thinks it's T1 or E1) is determined by the contents of a EEPROM.

My theory right now is that something in firmware looks at what the board identifies itself as, and decides how to set something in an FPGA that produces the clocks. Does this seem feasible?

Also, what other methods could it be using to get 1.544mhz and 2.048mhz from

50.000mhz?

The framing IC's in question are Dallas/Maxim DS2152L (T1) and DS2154L (E1). I have datasheets if anybody wants to have a look.

-C

I don't know if this what they did but:

50MHz / 1.554MHz = 32.3834

If you divide by 32 most of the time but 23 times every 60 cycles you divide by 33, you get 32.383333. This sort of fractional divider can get you quite close to the desired frequencies. It is a matter of how many bits you wish to use up in the extra counters required.

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kensmith@rahul.net   forging knowledge

That sort of logic goes great in a FPGA. But there is likely to be a lot of jitter in the output clock. (Great long term frequency if you use enough low bits.)

My guess is that the T1/E1 chips are providing a clock locked to the received data stream. It's common to use that clock to drive the transmit side. That makes the transmit data rate an exact match for the telco office.

Clocking on T1 can be "interesting". There are various modes/options.

One simple case is what I described above. The phone companies have an elaborate clock distribution system to ensure that they can send bits from X to Y and the clocks at both places will be the same.

Another mode is where the transmit end provides the clock and everybody downstream locks to it. (You can run 1.543999 in one direction and 1.544001 in the other.)

If you look at the right place, you can find the next layer of protocols where they add/drop a bit occasionally to handle the case where two phone companies both think they own the one true clock and you want to use a T1 line between them.

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It's been many years. I could easily be confused.

The interesting case is where you have a connection between two phone companies. They each have their own master clock. They will be very very close, but not an exact match.

There is a mode that puts some info into the framing bits. It basically steals some of them for a low bandwidth channel. I think the idea I'm trying to remember is that there was some stuff in that channel that would say, roughly, "drop a bit now", or "insert this bit now". ("now" was probably the end of the next frame.)

Suppose you go from customer X to phone company A to phone compan B to customer Y. X locks onto the clock from A. Suppose that's slightly faster than B. B occasionally removes a bit and puts it into the framming channel. With that info, Y can reconstruct what X was transmitting.

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I can't see any way to get a clean 1.544 or 2.048 MHz from 50 MHz. You can get the frequency as close as you want but you will still have up to 10 ns of jitter. Phone companies are usually not that sloppy with clocks.

Besides, unless your 50 MHz crystal is a lot fancier than you have mentioned so far, it isn't good enough for phone company timing.

My guess is that your board is getting the clocks it needs off the backplane.

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I think you meant 1.544, but I get the idea.

Interesting. This doesn't sound like the sort of thing that could be implemented by cascaded flip-flops though. (since that would only produce an output of (input clock/some even integer), not something fractional, right?

I can't find any chips on the board that appear to be fancier logic (ie: counters) that would be doing this. There's some dual flip flops, some octal flip flops, and a couple of 16-bit edge triggered flip-flops, everything else is not likely suspects for clock division (FIFO, SRAM, buffers, serial controllers, etc)

I may have to start taking continuity measurements to see where those signals are coming from....yuck. The board in question is mostly fine-pitch surface mount, some of the FGPA's having 240 pins each. Time to buy some needle-tip probes and set up my luxo magnifier.

I've thought of that, but I don't think it's the case because the board I'm working on would generally be on the phone company end. That and its setting for transmit clock is "Local Timing". It can also be set to "Loop Timing" which is what you were referring to. It also supports a method called SRTS, where data is embedded in ATM cells that gives the difference between source timing and some network timing reference, and allows timing reconstruction at the far end. (or at least that's my understanding)

I'm going to have to start probing around, I think. I may try making the board think it's the other one and see if it automatically switches over the timing to the chips. Might not work, but worth a try.

k8jlf posted:

I've thought of that, but I don't think it's the case because the board I'm working on would generally be on the phone company end. That and its setting for transmit clock is "Local Timing". It can also be set to "Loop Timing" which is what you were referring to. It also supports a method called SRTS, where data is embedded in ATM cells that gives the difference between source timing and some network timing reference, and allows timing reconstruction at the far end. (or at least that's my understanding)

I'm going to have to start probing around, I think. I may try making the board think it's the other one and see if it automatically switches over the timing to the chips. Might not work, but worth a try.

For what it's worth, the CO DS1 rate mux internal clock is usually synchronized by a 64kHz signal having bipolar violations at the byte boundary. D4 bank type mux's can be optioned to run on their internal Stratum 4 clock (+- 50 bit/s). You may have better luck if you can find that option and set it.

What equipment did your framer card come from?

Don

hmurray posted:

(snip)

That doesn't sound like any protocol I've seen used. Perhaps you are talking about a "frame slip" which can happen if one terminal end is experiencing clock/sync problems.

All central offices synchronize their digital equipment to a source traceable to a Stratum 1 clock. In practice you will normal never see a frame slip unless that link is severed and the backup link to a second Stratum 1 clock is also dead. The days of hierarchical sync between offices is long gone.

Don

By the way, what is the frequency of the crystal? I believe I saw an earlier post that it was 50 MHz. Could it be 50.432 MHz?

Don

(Replies inline)

snipped-for-privacy@aol.com wrote

That's the sort of thing that would come off a symmetricom box or other CO time source, right? I was reading something like that in the manual for a symmetricom timeXpander (clock distribution unit)

D4 bank

That gives me an idea. The unit in question does have built in Stratum 3/4 clock cards. It's conceivable that timing is being received over the backplane from those. But I don't think that would account for how the board makes either 1.544mhz or

2.048mhz clocks.

It's from an ATM/Multiservice concentrator of sorts. Takes blades with various interfaces, T1/E1/DS3/E3/OC3/STM, etc, and transports over ATM.

To answer your other question: I believe that the crystal is 50.000Mhz. It is made by CTS corp, and is model "MXO45HS" and is marked "50M000". Going from their datasheet for that part, that means 50Mhz on the dot.

Ok, while we're on that subject, what does the stratum 1 clock source generally consist of? What stratum would timing derived from GPS generally be regarded as? How about a rubidium clock as found in some cellular base stations? (I have one of these that I was thinking of trying to set up as a timing source for my lab.)

It is likely it is inside the FPGA but you could do it in flip-flop packages if you really wanted to on a 74HC74, both the "D" and "R/" inputs have to be high when the clock rises to make the "Q" output go high. This you can make an AND / NAND gate of sorts from the 74HC74. You just need a lot of chips to get many bits if you want to go this way.

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kensmith@rahul.net   forging knowledge

That's the answer I think I'm going to go with for now, and would make sense since it would allow it to be determined by something in firmware that looks at what the board is. I'll do another cursory check to see if there's a jumper or resistor different anywhere, then go with the firmware idea. (The firmware that loads to the FPGA's as well as the boot ROM is identical between the two boards, but there is another ROM which contains just the device ID of the board so it knows what to load as.) Changing that along with the framers and the resistors related to line impedance may do the trick.

Is it even possible to do fractional clock division using flipflops? (not that I think they really did it in this case) Normally I think of cascaded flip flops as divide by 2, divide by 2, divide by 2, and on and on. But you can't get 1.544 or 2.048 this way from 50.000Mhz.

Fractional divides can be done using the "S", "R" and "D" inputs of a D flip-flop to perform logic. The circuit ends up with a lot of flip-flops in it though.

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k8jlf posted:

That doesn't sound like any protocol I've seen used. Perhaps you are talking

Ok, while we're on that subject, what does the stratum 1 clock source generally consist of? What stratum would timing derived from GPS generally be regarded as? How about a rubidium clock as found in some cellular base stations? (I have one of these that I was thinking of trying to set up as a timing source for my lab.) >>

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Stratum 1 is an atomic clock having aq bunch of requirements; I believe the
frequency stability is 1 part in 10E-12.

Many Telco timing systems use GPS as a Stratum 1 traceable source for
synchronizing a local Statum 2 or 3 clock.

Don

hmurray posted:

hmurray posted:

It's been many years. I could easily be confused.

The interesting case is where you have a connection between two phone companies. They each have their own master clock. They will be very very close, but not an exact match.

There is a mode that puts some info into the framing bits. It basically steals some of them for a low bandwidth channel. I think the idea I'm trying to remember is that there was some stuff in that channel that would say, roughly, "drop a bit now", or "insert this bit now". ("now" was probably the end of the next frame.)

Suppose you go from customer X to phone company A to phone compan B to customer Y. X locks onto the clock from A. Suppose that's slightly faster than B. B occasionally removes a bit and puts it into the framming channel. With that info, Y can reconstruct what X was transmitting.

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Two telcos, each with their own clock, and each of them separately
synchronizing their clock from a source traceable to ANY Stratum 1 clock, do
not need to directly synch to one another.  The modern system method is called
pleisiochronous operation.  Neither office will drift in frequency enough to
force a frame slip.

DS1 does not use bit-stuffing for frequency maintenance.  Bit-stuffing used to
be required in the DS3 multiplexing scheme of muxing 28 DS1s into a DS3 (44.736
Mbit/s as I recall).  Prior to the telco network becoming extensively digital,
each terminal end of a DS1 path ran on it's internal clock for transmitting,
and de-multiplexed using timing recovered from the received signal.  Because
each DS1 could vary as much as 50 bits per second, the DS3 frame format
included time-slots that were used to put "1" bits in, or leave them "0."  In
this manner they maintained the average frequency of the DS3 signal.  *Not*
done in the DS1 bitstream.

The DS3 stuff-bit time slots have been put to a better use (look-up C-bit
Parity).

Don