Hi,
Considering me a newcommer to FPGA world. I am trying to use Virtex 4FX series for a synchronous design, meaning i will be using only one clock for whole design. Obviously if the main clock is running at 100 MHz, i would have software components on FPGA running at different clock speed like 80 Hz or 200 Hz. To acheive this i would have to divide the system clock. Xilinx suggest to use DCM for this purpose but to me it is confusing as it is location dependent. Does it mean i have to move my logic some how to the same area where DCM is or did i interpretate it wrong. Plus DCM out put clock can drive multiple software components. is it true?
Thanks