DCM and Clock

Hi,

Considering me a newcommer to FPGA world. I am trying to use Virtex 4FX series for a synchronous design, meaning i will be using only one clock for whole design. Obviously if the main clock is running at 100 MHz, i would have software components on FPGA running at different clock speed like 80 Hz or 200 Hz. To acheive this i would have to divide the system clock. Xilinx suggest to use DCM for this purpose but to me it is confusing as it is location dependent. Does it mean i have to move my logic some how to the same area where DCM is or did i interpretate it wrong. Plus DCM out put clock can drive multiple software components. is it true?

Thanks

Reply to
Fizzy
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You call it "synchronous design" but then you mention 80 MHz and 200 MHz. Be careful with multiple clock domains. Any domain crossing is fraught with danger. A DCM usually drives a global clock line, which -as the name implies- can drive anywhere on the chip. Somebody else told you specificlly to do more reading and studying first, and I concur... Peter Alfke

Reply to
Peter Alfke

Well when i said synchronous, i ment the 80 and 200 Hz clock will be extracted from the global clock. Now can i use DCM at that point where i want 80 Hz derived from system clock. Previously i know its been done by dividing the system clock , Reading DCM i think it can do the same job without clock skew and jitter. I wanted to know if DCM placment does have any impact ???

Reply to
Fizzy

Just to be clear, since you say you are dividing 100MHz to get 200 Hz. Are the "80" and "200" really Hz, or MHz? If they are Hz, then a DCM won't help.

Reply to
Duane Clark

Fizzy schrieb:

DCM ist for "high-speed stuff" only. 24 MHz++. Ok, there are few exceptions. But to cut this story short. Use ordinary counters to get 80 Hz and 200Hz.

Regards Falk

Reply to
Falk Brunner

Duane,

Location (in this case) doesn't matter. The tools take care of the timing through the use of the global clocks.

In your case, your divider will have to divide by a very large number, to get to 80 Hz. DCMs can not do that. The CLKDV is good for 1.5, 2,

2.5, 3, 4, 5 ....15.

The CLKFX is good for M and D ranging from 2, to 31.

The input frequency must be greater than 24 MHz, or if using the DFS only, greater than 1 MHz - and the CLKFX must then be greater than 24 MHz.

Aust> Fizzy wrote:

Reply to
Austin Lesea

Then if that's the case DCM is only for high frequency what are my option to have low skew and jitter on clock. Actually let me explain a little bit so i can ask the question properly. I am designing an application which will run on 200 Hz (Hertz just). I ahve system clock running at 100 MHz. I have PowerPC405 running at 100 Mhz. The custom design is connected to PPC405 through PLB. What is the best way to clock now. What i was thinking earlier is to have on chip clock comming to DCM and extract the required clock from it (200 Hz) but you guys saying its not possible so waht are my options?

Reply to
Fizzy

Fizzy,

Divide it down using CLB's which implement a synchronous counter.

Use the output as a clock.

Or use the carry output as a clock enable.

Aust> Then if that's the case DCM is only for high frequency what are my

Reply to
Austin Lesea

Can i use multiple DCM to extract the required frequency ?? like Dasiy chain

Reply to
Fizzy

Fizzy,

No, you can not (cascade DCMs to get 80Hz).

The DCM internal structures must be able to fit an entire clock period in the delay lines to operate.

The largest delay line will hold a 24 MHz period (~ 40 ns).

To hold an 80 Hz period would take far too large a structure.

That is what counters are made for.

Aust> Can i use multiple DCM to extract the required frequency ?? like Dasiy

Reply to
Austin Lesea

Fizzy schrieb:

What is the problem?

100 MHz / 500000 = 200 Hz 100 MHz / 1250000 = 80 Hz

No jitter. As easy as it gets!

Use a *zensored* counter!

Regards Falk

P.S. Of cource, dont use the 200 Hz out of the counter directly as a clock. Run the logic on the 100 MHZ and use a 200Hz clock enable. I gues the 200Hz is only for interupt generation?

Reply to
Falk Brunner

How about the output x and 2x of a DCM? Are they synchronous enough to make resource timesharing without fancy synchronization bridges? How should I express that in VHDL? Say:

input A, B output A', B'

A' := do_something(A) on every even clk2x pulse B' := do_something(B) on every odd clk2x pulse

Best regards Piotr Wyderski

Reply to
Piotr Wyderski

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