virtex-5: can't use DCM (too low input frequency)

Have you looked into DDR flip-flops? Those should allow you to read data coming in on both clock edges at the regular clock frequency. Check out the Virtex 5 IDDR input primitive.

Regards,

-- Hauke D

Hi Giulio, So, your input frequency is 6MHz. The wizard tells you that "DFS Low Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps you should use your DCM in DFS Low Frequency Mode. HTH., Syms. p.s It's Hz not hz.

aps

If I remember right (I am at home on this beautiful sunday) the output frequency then must be above 19 MHz. So you would have to multiply by 4 and then use a flip-flp to divide by 2.

The suggested use of the DDR input seems to be best, it gives you two parallel bits at the 6 MHz frequency. If you prefer 12 MHz, I could mention "my" frequency doubler from "six easy pieces".

There are several solutions... Peter Alfke

aps

I believe the problem is that the clock doubler is one of the DLL (not DFS) outputs, where the minimum input frequency, even in low frequency mode, is 19 MHz.

Regards,

-- Hauke D

I see your point. I suggest multiplying by 4 and then dividing by two using clock enables in the fabric. Cheers, Syms.

Unfortunately, I can't use 2xClockOutput in DFS Low Frequency Mode :( Thank you all for the help, I'll try both ways:

1) using a DCM and dividing the 4x output by two (can I use another DCM for this purpose?) 2) using IDDR flip-flops

Giulio

n

rhaps

Giulio, I would advise against using a second DCM: It creates additional jitter, and it makes it reallycomplicated to solve your inherent phasing problem: When you multiply by 4 and then divide by 2, you have a 50% chance of picking up a wrong phase relationship between your 6 and 12 MHz clocks. Here is one solution: Use the 24 MHz clock to generate a delayed version of your 6 MHz clock. Then control your divide-by-2 flip-flop such that it can change state only when both your 6 MHz signals have the same level. Use an XOR. I think the DDR method, or "my" frequency doubler are better solutions. Peter Alfke

haps

So? Instead use the CLKFX output in maximum range mode to provide a 24MHz clock and read in the data on every second clock cycle. (Do NOT divide the clock using DFFs, instead use clock enables).

Kolja Sulimma

Hi Peter, The DDR method makes the logic more complicated. You have to deal with two samples every clock cycle. As for "your" frequency doubler, in the right hands it can be a useful tool. However, with a simple synchronous solution available using a DCM, I wouldn't recommend this path, especially for beginners. YMMV, Syms.

If you can't use the CLKx2 because the output frequency is too low for the DCM, you wouldn't be able to use a CLKx4 output to drive another DCM in divide-by-2 mode because - surprise - the output frequency of the 2nd DCM would be too slow.

I second the use of clock enables rather than DFF based divider and the XOR phase control method:

If you toggle one flop with 6MHz and reregister that flop at the 24MHz clock, the XOR of those two registers will always be asserted the clock phase after the 6MHz edge. Either use that as a "data is valid" clock enable for a downstream-only system or use that signal to reload a 2-bit counter and decode the timeslot *before* the 6MHz edge for the clock enable if you need the I/O to be aligned to the 6MHz clock.

- John_H

Ahem - sorry, frog in my throat...

I second the use of clock enables rather than DFF based divider and I also second the XOR phase control method:

I didn't mean to add any confusion :-)

"

This whole subject looks like a good basis for a creative appnote. Peter Alfke

Hi Giulio, Does the camera generate the clock or does the FPGA make a clock to drive the camera? Thanks, Syms.