Dear
I am synthesizing and mapping following examples (counters) into Vertex II pro with ISE6.3. Both of them are working okay in Modelsim.
And I wish to verify them after mapping using Chipscope Pro - Inserter and Analyzer.
Version 1 is okay.
Version 2 is a version, which has "rst" input signal. Problem is that version 2 not okay in ChipScope Pro, saying that " INFO - Device 2 Unit
0: Waiting for core to be armed ".Both of them are error-free and warning-free during mapping process. What is the problem in version 2? Is it really a problem? How can we verify the version 2?
Thankyou again :) Regards
----- Version 1 ---------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity top is port ( clk : in std_logic := '0'; cnt : out std_logic_vector(3 downto 0) ); end top;
architecture behave of top is signal counter : std_logic_vector(31 downto 0):= (others => '0'); begin process(clk) begin if ( clk'event and clk = '1' ) then counter