simulatable but not synthesizable (verifiable)

I don't understand this because I don't know about ChipScope Pro, but I do understand why your VHDL is wrong.

rst_tmp is required to reset the counter on both rising and falling edges of the clock. This is clearly inappropriate for any real devices.

This is strange - the synthesis tool should reject it, or at least issue a warning for the incorrect coding style.

If you want the reset to be synchronous, put it into the clocked-logic part of the process so that it is tested synchronously:

process(clk) begin if ( clk'event and clk = '1' ) then if rst_tmp = '1' then counter '0'); else counter

Jonathan Bromley schrieb:

It is an asynchronous reset. I think he should have rst_tmp in the sensitivity list.

cheers Gunther

Yes, I missed it. Reset signal "rst_tmp" should be within sensitivity list. Below is the correct one.

BTW, my goal is to "verify" its functionality (of the "internal" 32 bit counter) in a real FPGA chip.

In version 1, I am able to "see" the behavior of internal signals in waveform (exactly same as simulation), using "Inserter" and "Analyzer" in ChipScope Pro. The difference between version 1 and 2 is the 'rst' input signal. In version 2, however, no waveform can be seen in "Analyzer". That was a problem :)

If someone has idea how to set up ChipScope Pro environment for this case, let me know.

Thankyou so much. Regards

------- Version 2 ------------------------------=AD----- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity top is port ( clk : in std_logic; rst : in std_logic ; -- additional 'rst' input cnt : out std_logic_vector(3 downto 0) ); end top;

architecture behave of top is signal counter : std_logic_vector(31 downto 0):=3D (others =3D> '0'); signal rst_tmp: std_logic :=3D '0'; -- initialization begin rst_tmp