asynchronous counter an Xilinx FPGA for a newbie

Your synthesis tool does not synthesize:

But it synthesizes it with a different sensitivity list: process(Rst, Load, QREG)

If you simulate (before synthesis) the process with this sensitive list you will notice the loop if LOAD='1' and rst='0'.

I'm not sure if you want a latch, but a flipflop solves the problem. Replace

with elsif rising_edge(Load) then

Egbert Molenkamp

"Georges Konstantinidis" schreef in bericht news:401ab556$0$777$ snipped-for-privacy@news.skynet.be...

Why do you want to do an async counter? No clock available?

What is the implementation error? (Actually, I know what it is -- but I want to know what you think it is.)

Think about:

What happens if neither Rst nor Load are asserted?

What do you mean by saying "asserted"? "Andy Peters" a écrit dans le message de news: snipped-for-privacy@posting.google.com...

message news:...

number

design. I

Try this:

library ieee; use ieee.std_logic_1164.all;

entity counter is port( Load: in std_logic; Rst: in std_logic; LED: out std_logic_vector(0 to 7));

end counter;

architecture behaviour of counter is begin

cnt : process(Rst, Load)

variable count : std_logic_vector(7 downto 0);

begin

if (Rst = '1' then) then count := "00000000"; else if (Load'event and Load='1') then count := count + 1; end if;

LED

"Asserted" means "put into the active state."

It's a very common term. It's useful because it nicely ignores the detail of whether the signal is active low or active high.

Thanks for the info. "Andy Peters" a écrit dans le message de news: snipped-for-privacy@posting.google.com...

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Hello Andrew, I was endeed using a "normal I/O port" which is synchronous or asynchronous according to the datasheets. I should be able to use it. Or I miss something. I found also a template in ISE called "debounce circuit" which seems to work. In any case I will also try what you said Thanks everyone for you cooperation, Georges.

"Andrew Greensted" a écrit dans le message de news:bvlerm$crt$ snipped-for-privacy@pump1.york.ac.uk...

First of all , when you say that you are implementing a counter, what are you going to count???????

assuming whatever you are going to count is A, then use this code to increment the count if A'event and A = '1' -- or A = '0' whatever be the case count := count + 1; end if;

or else you might endup counting something else or endup in a infinite loop as u see to be now.

I want to count pulses coming from outside the FPGA (Spartan IIe on the Burched board) and displays the valus on a 7 digits segment. I tried already your code. the synthesis works, but not the implementation design. I created an UCF file to assign the pin, maybe this file creates problem. I do not know at which moment of the process I should assign the pins. Georges.

"Sajan" a écrit dans le message de news: snipped-for-privacy@posting.google.com...

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I think this boils down to what is considered good design practice. If you want to count the edges of a single input line, then it really should be considered as a clock input, and therefore you should be using a dedicated clock input pin.

If you use a standard IO pin, then ISE will grumble about using it to drive clock inputs. If you're stuck with this setup, then you really should be sampling this IO line. If you're expecting a fairly low input frequency, and a long mark and space time (high and low time) then this should be easy enough.

In a nutshell. If you where going to do this in good old fashioned 74 series, you'd plug the signal you want to count into the counter clock input. For similar reasons you should connect the same signal into the FPGA clock input.

Andy

P.S. Chances are some> Hello Andrew,

(snip of VHDL code)

If you write it in Verilog I might be able to tell you.

I don't think it looks like an asynchronous (ripple) counter, though. It might be that you can't make ripple counters on the system your synthesis is targeting.

-- glen