can bus protocol on fpga

Have you used Google to look for one?

There's a CAN block on Opencores

Also a PCI bridge.

Alan

I have seen that site but the link is broken, only the sources in verilog are available. Could you check for me if you caa get the vhdl cores with your PC, maybe I can't because of my computer. thank you

I think the VHDL core is dead. Why MUST it be VHDL? If your tools don't allow a mixed Verilog/VHDL design use a netlist of the core. Works fine for me.

Andre

mungam wrote:

Yes I can do it with verilog but I've never read verilog, so i will have to learn it. Did anyone try to use this core before?

I'm using the core in a wishbone environment and it seem to work fine, haven't done too much testing though. It is not well documented, but you can get a SJA1000 datasheet from Philips, that helps a lot. Get the source from CVS, afaik they are more up to date. Unless you want to make changes to the core some very basic verilog skills are enough. Here's my component declaration for the wishbone variant:

component can_top port ( wb_clk_i : in std_logic; wb_rst_i : in std_logic; wb_dat_i : in std_logic_vector(7 downto 0); wb_dat_o : out std_logic_vector(7 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_adr_i : in std_logic_vector(7 downto 0); wb_ack_o : out std_logic;

clk_i : > Yes I can do it with verilog but I've never read verilog, so i will

Hello Andre, Thank you very much for your answer, you seem to be very well up to date on this topic. I have download the verilog sources from opencores and the compilation was successfull. If I understand well, this core is used to do the same work as the sja

Thank you

Adrien

Hi Adrien,

Maybe this is already clear to you, my apologies if so, but the CAN protocol block and the PCI bridge are both peripherals which are connected to the wishbone bus. Typically there will be a bus master such as a micro-processor core (or equivalent state machine) which will drive the bus to set-up the slave peripherals, monitor the status registers of the slaves, identify when some data needs to be moved from one to the other, and perform the move or configure a DMA bus peripheral to do the move.

So your project is not simply a case of connecting the CAN block to the PCI block, you will also need a controller of some sort sitting on the bus (micro-processor core etc).

Not a trivial project, but not impossible either by any means.

Alan

The opencores pci bridge can act as a wishbone bus master, so you can connect it directly to the CAN core. I don't know if you use your own PCI core, if so, you propably have to write a wishbone interface for it.

Connecting the core to a CAN transceiver is simple. If you are using an FPGA without 5V tolerant I/Os use a 3.3V powered transceiver or a level converter.

Weeeeeeekend!!

Andre