CPLD + CAN bus

Falk Salewski wrote: : Hello everybody,

: I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make : it easy I would like to use a ready to use CAN-bus driver chip (as much of : the : protocol implemented as possible). Any suggestions? How many of the CPLD : resources does it take to initialize/communicate with the CAN-bus driver : chip?

There is a CAN Protocoll Controller at

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Thank you very much for your reply.

However what I am looking for is how difficult is it to connect a CPLD to a CAN-controller chip like the SJA1000

and how many of the CPLD resources it takes to initialize/communicate with this CAN-controller.

bye Falk

"Uwe B> : Hello everybody,

You'll need to setup the registers [either a rom in the CPLD, or a Serial EE holding the init values, to BUS], and then be able to poll messages, and manage TX packets (which come from where ?).

All of these are not CPLD-centric tasks, so why not use a small uC instead - or even better, choose a uC with CAN on chip ? If you have the XC2C256 there already, needing > 128 MC for other tasks, then you could use a small portion, for SPI-SJA1000 bridge, and then use a small SPI uC for the CAN manager/init. Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny

11-20pin packages. -jg

Falk Salewski wrote: : Thank you very much for your reply.

: However what I am looking for is how difficult is it to connect a CPLD to a : CAN-controller chip like the SJA1000 :

: and how many of the CPLD resources it takes to initialize/communicate : with this CAN-controller.

: bye : Falk

: "Uwe Bonnes" schrieb im : Newsbeitrag news:coensd$mh6$ snipped-for-privacy@lnx107.hrz.tu-darmstadt.de... : > Falk Salewski wrote: ...

Can communication needs some protocoll stack. Your question seems to be what implementing this stack in hardware needs with regards to hardware resources.

My guess is that the 2c256 is too small for that task.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

: All of these are not CPLD-centric tasks, so why not use a small uC : instead - or even better, choose a uC with CAN on chip ? : If you have the XC2C256 there already, needing > 128 MC for other : tasks, then you could use a small portion, for SPI-SJA1000 bridge, and : then use a small SPI uC for the CAN manager/init. : Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny : 11-20pin packages.

Perhaps PicoBlaze for CoolRunner-II could be used too...

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Thanks for the reply!

I realized four 8bit counters in the CPLD and just want to send this information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not thinking wether this is the optimal solution but if it is possible without an aditional uC (Project at university) I will have a look if I can store enough information in the CPLD for the initialization of the SJA1000 chip...

FalkS.

"Jim Granville" schrieb im Newsbeitrag news:mBCqd.13010$ snipped-for-privacy@news02.tsnz.net...

I thought the protocoll stack is already implemented in the SJA1000 and I just have to write to some kind of send buffer and read from a receive buffer...

Falk

not

Quiz: How many macrocells is needed to initialize MMC card (nonSPI mode) and configure and FPGA from bitstream file on the card?

Answer: 20 PLD macrocells!

256 PLD cells can be alot. depends how they are used :)

but I would not go with SJA1000+PLD (unless restricted to those component by definition) waste of time and human resources

Antti

No file system support (I assume) and no partition support. How do you write the bitstream as row data ? cheers, Aurash

--
 __
/

without

and

KISS :) format the MMC card, then copy download.bit to the card! thats it. simple as that. if once written can be overwritten without the need to format the card.

Of course I do have some utilities to write directly to the card (in hidden area) too, but those arent even necessary

Antti

First, find some working SJA1000 software, in any uC family will do. Search also for the 82C200, which is the older sibling of the SJA1000. Philips will probably have some 80C51 examples. Then, look to move that function into the CPLD. To give your tutor some real numbers, assemble JUST the code for init & simple Echo, and print the LINK MAP, to show how much RAM and CODE space is needed. [eg it might be 5 bytes of RAM, and 275 Bytes of Code]

I think I saw recently a CAN controller [SJA1000 like], that could as an option, 'wake up' in simple peripheral mode, IIRC using a Serial EE to config. That would be another 'no code' alternative.

-jg

"Falk Salewski" schrieb im Newsbeitrag news: snipped-for-privacy@uni-berlin.de...

it

the

If you do so, use a uC with integrated CAN controller. But then you dont need a CPLD anymore. I dont see the point of using a CPLD with CAN. You CAN do it ;-) of cource.

Regards Falk

"Falk Salewski" schrieb im Newsbeitrag news: snipped-for-privacy@uni-berlin.de...

not

It CAN be doen this way, but

-- it is more expensive.

-- more complicated

Regards Falk

"Antti Lukats" schrieb im Newsbeitrag news:cofco1$b9n$05$ snipped-for-privacy@news.t-online.com...

as

Nice trick, but Iam afraid the CAN bus protocoll is a LITTLE bit more complex.

Regards Falk

simple

LOL, yes just a little :)

well only wanted to point out that 256 cells PLDs SHOULD be large enough for register init sequencer to initialize some CAN interface chip like MCP2515

antti

If you change the SJA1000, to the Microchip MCP25020, that has 8 I/O and on chip config registers so can 'wake up alive'.

Simplest scheme to tranfer counter info, from a CPLD, would be a nibble-ram map, where you allocate 4 of the I/O as Address, and

4io as read-back nibble. A Write-Read CAN transaction, then Sends Address, and recovers one firmly identified nibble, and 16 nibbles can map 8 bytes of info.

-jg