I tried examining the V4 LVDS input IBIS models last night.
Loading them into Edality's free IBIS viewer gave me the following warnings for the LVDS_25 buffer models (v2.2):
IBISCHK3 V3.2.8
> Checking virtex4.ibs for IBIS 3.2 Compatibility...
> WARNING - Model LVDS_25: POWER Clamp : Typical value never becomes zero
> WARNING - Model LVDS_25: POWER Clamp : Minimum value never becomes zero
> WARNING - Model LVDS_25: POWER Clamp : Maximum value never becomes zero
Examining the clamp tables, it appears the input buffers will be sourcing rail current, significantly hauling up the signal levels on an LVDS driver connected to them.
Anyone else seen this? Is this correct, or are my IBIS reading skills too rusty?
Also, the DIFF_TERM input is modeled with a IBIS series element as a simple resistor (+/-20%) across the input.
Has anyone seen any documentation of (or measured) the input termination non-linearities away from 1.2V, other than the notes in Answer Record 13910, and the 2.5V VCCO supply requirements noted in Answer Records 17244 and 15633 ?
thanks, Brian