1. Home
  2. Field-Programmable Gate Arrays
  3. RocketIO MGT Clocking Arrangement!

RocketIO MGT Clocking Arrangement!

Dear All,

I am a little confused with regards to the clocking arrangement associated with the Xilinx Rocket IO MGT.

I want to use the MGT in Half Rate Mode with no 8B/10B encoding / decoding with a byte wide interface (actually 10-bit wide due to not using the 8B/10B).

I have the following clocks (as per page 54 of the Rocket IO User Guide [Vertex-II Pro]):

REFCLK > tied to the pre-DCM input clock (clkin) RXUSRCLK & TXUSRCLK > tied to the DCM output clock (div2) RXUSRCLK2 & TXUSRCLK2 > tied to the DCM output clock (clk0)

My question is which clock do I use to clock my data TO the MGT and conversely FROM the MGT?

The user guide says "Each edge of the slower clock must align with the falling edge of the faster clock", as a result it suggests that TXUSRCLK2 & RXUSRCLK2 are inverted so that clk0 can be used instead of clk180.

"Since clk0 is needed for feedback, it can be used instead of clk180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver's local inverter, saving a global buffer (BUFG)."

My second question is, if the answer to question 1 is TXUSRCLK2 & RXUSRCLK2 as suggested in the User Guide, is it permissible to invert the RXUSRCLK & TXUSRCLK's instead of inverting the TXUSRCLK2 & RXUSRCLK2 to assist with clock alignment in other areas in my design?

Many Thanks,

Simon

Reply to
simon.stockton
Loading thread data ...

snipped-for-privacy@baesystems.com schrieb:

Hello Simon,

1st question: For your user interface you should use the usrclk2. This clock depends on the data width.

2nd question: the relationship between the REFCLK and the USRCLK is not so important because you can use the FIFO´s and the clock-correction-codes. There is generally a delta time between the REFCLK and the USRCLK over the DCM.

Helmut

Reply to
Helmut

Helmut

Thanks for the reply.

Are you implying from your answer 2 that it is permissable to invert USRCLK instead of USRCLK2 thus still conforming to the "Each edge of the slower clock must align with the falling edge of the faster clock" but not "Since clk0 is needed for feedback, it can be used instead of clk180 to clock USRCLK2 of the transceiver with the use of the transceiver's local inverter, saving a global buffer (BUFG)."?

Simon

Reply to
simon.stockton

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.