How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
I'm restricted to 30Mhz LVDS clock input.  From this, I need to
generate 240Mhz to be used internally.  Restriction comes an ASIC that
I'm interfacing to.  What options do I have here?

Based on what I see in ds302 by Xilinx, I haven't found a clean (or,
any) solution.  Minimum clock speed I need is 32Mhz for DCM.  If the
min speed weren't an issue, I could cascade two DCMs - 4x and 2x - to
get 8x.  (I know, cascading is not ideal due to jitter).

Am I stuck?  The 30Mhz clock is actually for data coming in at 240Mhz
rate.

Is there any way out of this?


Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Use Frequency Synthesis mode driving the Fx output.
Then you do not have the min input frequency limitation, and you can
multiply and divide (simultaneously!) the input frequency by any
integer up to 32. So you just multiply by 8 and divide by 1 to get 240
MHz.
Peter Alfke, Xilinx Applications, from home

On May 9, 9:43 pm, snipped-for-privacy@yahoo.com wrote:
Quoted text here. Click to load it



Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Quoted text here. Click to load it

Hello Peter, thanks... could you tell me where it is documented?  I
remember that vaguely from
the Virtex(2?) days, but can't remember the details.  Also, but when I
tried to verify that using
core generator (I normally instantiate DCM manually instead of using
coregen, btw), it says

"The specified input clock frequency restricts your output frequency
to LOW frequency range.
Either change your input clock frequency or your M/D value to correct
this."

Is it a tool issue?

Thanks again.


Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Click on the Virtex-4 User Guide
http://direct.xilinx.com/bvdocs/userguides/ug070.pdf
Then read page 55 (in the center of the page) and pages 63, 74, and
75.
 In Frequency Synthesis mode, the Fmin limit (~30 MHz) applies to the
output frequency, not the input frequency. You should have no problem.
Peter Alfke

On May 10, 6:13 am, snipped-for-privacy@yahoo.com wrote:
Quoted text here. Click to load it



Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
After answering you from memory, I studied the data sheet more
carefully:
http://direct.xilinx.com/bvdocs/publications/ds302.pdf

You need to be in High Frequency Mode, where you can generate Fx
output frequencies between 210 and 300 MHz, as shown on page 35 at the
top.
One inch further down, there is a Fmin spec of 50 MHz which you can
ignore. It was put in there as a precaution against excessive jitter
on the input.
Hopefully, your clock does not have excessive jitter.
Peter Alfke


Quoted text here. Click to load it
Guidehttp://direct.xilinx.com/bvdocs/userguides/ug070.pdf
Quoted text here. Click to load it



Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Peter - thanks again.

So, I can use 30mhz CLKIN to create CLKFX @240mhz (M=8,D=1)...
but can I use CLKFB to remove the insertion delay here?  All documents
I looked at talk about
CLKIN out of the range _and_ using only FX outputs (with no CLKFB
hooked up).  I can see
why that's the case.

If that's the case, how do I receive the 240Mhz data that's
synchronous to the 30Mhz input clock
- the delay from the pad thru ibufg, dcm, bufg is not quantified, I
don't believe.  I wouldn't know how
to align the clock to the data.  (In the lab, I can, but not over
temp, volt, etc...)  I mentioned receiving
the data in the original post, maybe it got missed.






Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Here is what you can do:
Without any DCM feedback, there is no defined phase relationship
between your 30 and 240 MHz.
If, however, you buffer the CLK0 output and feed it back to the DCM
input, the rising edge of every eighth 240 MHz cycle will be aligned
with the rising of your 30 MHz input at the point where it meets the
DCM. Any further synchronization is up to your creativity.
Peter Alfke

On May 10, 12:00 pm, snipped-for-privacy@yahoo.com wrote:
Quoted text here. Click to load it



Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
Quoted text here. Click to load it


In addition to Peter comments, you might want to read XAPP265 (High-
Speed Data Serialization and Deserialization, 840 Mb/s LVDS).

Patrick


Site Timeline