How can I get an output clock phased align with the input clock.

Hi Chris,

Basically you need a c>Hi,

snipped-for-privacy@hotmail.com (chris) wrote in news:33923a80.0406020327.20fde6f3 @posting.google.com:

Can't you just use two DCMs as shown in the FPGA datasheet to remove the skew caused by the buffer and PCB delays?

Take a look at Xilinx App Note 174 - Figure 11 (Board Level Deskew of Board Level Clock between Multiple FPGAs.

The jist is that after your master FPGA generates its output clock at the PWB level, the signal is routed back into the FPGA BUFG input and is used to drive the FB input of the originating DLL/DCM. This is parallel for the Master FPGA as well as slaves.

Traces should be matched at the board level. Also, make sure you think about the reset philosophy of the multiple FPGAs on the board. This usually requires a little thought, since resets and clock availability are tightly coupled in synchronous design. Usually, the master FPGA also distributes a "reset" signal to apply to slave DLLs.

-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

Colorado based Xilinx Design consultant

email : snipped-for-privacy@rtc-inc.com web :

Hi Luc,

The master clock frequency is around 100MHz and is coming from an ADC.

Christophe.

Chris,

Do you need other frequencies in your FPGAs derived from this clock? Is it single ended or differential? What skew do you need to anticipate?

PLease let me know,

Luc

Hi Christophe,

Look on the Lattice website. They have released the part that I mentioned before. Look under clock management. Very easy interface, a lot of features, flexible profile management, etc.

Best regards,

Luc