All,
I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated.
I have a board designed around the EP1C6 Cyclone device. The Quartus programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able to initiate programming the device over the JTAG port, but Quartus gives me an error CONF_DONE failed to go high on device 1.
I reviewed the Cyclone datasheet, and 13-19 in particular, "JTAG Configuration of Single Cyclone FPGA."
This diagram does not show CONF_DONE going to the programming header.
Why is Quartus complaining that CONF_DONE isn't going high when that signal isn't supposed to go to the programming header? More importantly, is there anything I can do to circumvent this problem?
Many thanks,
-Nevo