Altera Quartus Error How to track donw.

Jan 06, 2005 5 Replies

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GMM50 21 years ago

Hello:

I'm entering a desing in to Altera's Quartus II 4.1 using block diagram files as the input mechanism.

When I try to compile I get the following message...... Internal Error: Sub-system: CDB_SGATE, File: cdb_sgate_wys_ygr.cpp, Line: 4111 cdb_is_connected(b_iterm) Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version ...............

The error is probably something I've done as I created the schematics. My question is how to track the error down?

The design is heirarcail and I've tried deleting functional blocks. When I do I get different error messages because signals are now missing.

What steps to take.

Thanks George

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Subroto Datta 21 years ago

Hi George,

Please use mysupport to submit a problem request along with your design. It will not be possible to track down this problem without the project and the design files.

Subroto Datta Altera Corp.

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GMM50 21 years ago

I did.

Last time I used MySuppory it took 6 weeks for a reply and the reply was "Is this still a problem" and I answered Yes. That was last November.

George

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Subroto Datta 21 years ago

George,

Please email me the Problem Report number and I will get the design form the supportfolks.

Sincerely, Subroto Datta Altera Corp.

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GMM50 21 years ago

I found the problem!!!

The design targeted a Cyclone FPGA. I generated a 9 bit counter lpm_counter0 and used my signal INC_WF_ADDR as input to increment that counter. That signal was missing form the design.

I changed device to ACEX1K and problem was reported instead of the internal type crash. I sourced the signal changed back to Cyclone and the desing now compiles.

George

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GMM50 21 years ago

And to close this issue Installing the Quartus II V4 sp2 resolved the crash and identifies the problem.

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