Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Another simple DCM question
I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two clock sources have a fixed phase relationship. I routed a single reset signal to...
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17 years ago
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ModelSim VHDL Pragmas
Hi All, In one of my VHDL designs I have a section of code that I want different versions for synthesis than for simulation. Currently I just comment out one section and uncomment the other, but I had...
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17 years ago
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EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07
ELECTRONIC DESIGN PROCESSES (EDP) 2007 April 12 & 13, 2007 Monterey Beach Hotel, Monterey, California The Electronic Design Processes (EDP) provides a forum for a cross- section of the design...
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17 years ago
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Xilkernel-EDK8.2
Hello, I try to compile an Avnet example (PPC BOOT Loader Design) with my FPGA card. when i build the projet i get the following error message: ERROR:MDT - xilkernel () - bash.exe: warning: could not...
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17 years ago
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xilinx ise/edk/modelsim - what does compilation really do?
I have some questions about xilinx ISE/EDK and modelsim simulation. I'm looking for advice/pointers. I'm an reformed software guy, and my perspective is from using a lot of open source tools like...
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17 years ago
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Complex Baseband
Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying the input stream (12 bits) from the ADC with Sin and Cosine outputs of a DDS and...
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17 years ago
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"undeclared here" error and undesired file persistance in Xilinx Platform Studio
I have a C program I'm developing for the Microblaze SOC processor. I'm using the Xilinx Platform Studio ver. 8.2.02. I had included in the project a particular *.c source file, then removed it. The...
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17 years ago
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RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
Hi, The VHDL standards community needs feedback from VHDL users. Currently the Accellera VHDL TSC is working on enhancements to add classes/OO, Randomization constructs, and Functional Coverage with a...
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17 years ago
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Webpack 9.1 Service Pack 3
Hello, did my update go wrong or does also a succeeded update of Xilinx Webpack with 9_1_03i_lin.zip still display "Release Version: 9.1.01i"? Webupdate reports now : " There are no updates to display...
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17 years ago
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Regarding connecting two Ethernet Mac Phy
Hi everyone, I have an FPGA board with two ethernet MAC interfaces. I want to connect both interfaces in a way that transmitter of one EMAC IF is connected with reciever of other and vice versa. I...
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17 years ago
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We need avnet fx12 mini module URGENTLY!
Hi all I'm a student of the UAM (University of Madrid, Spain). My TEA (pre thesis) is based on this board. I present it in 3 days, and I have broken the only board I have. I need desesperetly someone...
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17 years ago
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Some errors i dont know in XMD
Hi all I am trying running uClinux on MicroBlaze. Memory Test Demo is going all right. In XMD, I download the imagebin with the cmd "dow -data 0x24000000", and then "con 0x24000000". But got the...
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17 years ago
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Watershed Transform
Is there anyone who has created a VHDL, Verilong or Schematics "WaterShed Transform"?. It is an image transform and I am not sure if it is possible to implement it. Thanks, Pablo
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17 years ago
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suggestion for choosing the right FPGA for gigabit transciever
Hi, I need to chose between the Altera Stratix II GX or Stratix III GX and some Xilinx Virtex5 FPGA for an implementation of gigabit interface into a multi DSP system. Could you suggest pro and cons...
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17 years ago
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Problems with Xilinx Parallel III Cable
Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a programmer to use the Xilinx Parallel Cable III. I implemented the programmer 100% the...
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17 years ago
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