Field-Programmable Gate Arrays

Boot PowerPC on VirtexIIPro

Well I have a strange problem. I have a VirtexIIPro30 on a Sundance target. I use XPS 8.2.02 to create a design with a...

1 comments posted 19yrs

posted by pbantunez

1 comments posted 19yrs posted by pbantunez

RFC: VHDL testbench enhancements

Hi, Let me try this again. The VHDL standards community has been considering whether to enhance VHDL to add advanced te...

5 comments posted 19yrs

posted by jim

5 comments posted 19yrs posted by jim

QUIP write_verilog.c

Hi- I have been using the QUIP package and have one question regarding integration with SIS. I have been reading the qu...

0 comments posted 19yrs

posted by trackmanatISU

0 comments posted 19yrs posted by trackmanatISU

re-assemble bootloader for NIOS Processor

Hello, I want to recompile the bootloader for the Nios processor. The reason that I want to do this is: - I use an EPCS...

2 comments posted 19yrs

posted by Karel.Deprez

2 comments posted 19yrs posted by Karel.Deprez

Implement IIR Filter on FPGA

hi people, I'm designing filter system called IIR filter on the FPGA kit, but it doesn't work when I implement on FPGA....

6 comments posted 19yrs

posted by gordonfreeman1983

6 comments posted 19yrs posted by gordonfreeman1983

ISE 9.1i SP3 simulator problems on Linux

When trying to run the WebPack ISE 9.1i SP3 simulator on Linux (Gentoo, specifically), it always stops building the sim...

3 comments posted 19yrs

posted by koch

3 comments posted 19yrs posted by koch

X_OBUF and other error messages with ModelSim

I am trying to perform a Post-Translate simulation of a design, but I'm getting a huge number of errorts that are basic...

1 comments posted 19yrs

posted by mhs000

1 comments posted 19yrs posted by mhs000

Does the XC3S250E-VQ100 exist?

I have an application that is very space limited, and would like to use a Spartan XC3S250E in the VQ100 package. Even t...

6 comments posted 19yrs

posted by jshamlet

6 comments posted 19yrs posted by jshamlet

Dynamic Reconfig

Hello, I would really appreciate if you could give me some insight on the following -Can you guide me to a link/example...

2 comments posted 19yrs

posted by prasad.anirudh

2 comments posted 19yrs posted by prasad.anirudh

MGT Digital Receiver Oversampling

I started working with the MGT's recently on a V4 PCI-E development board. I am just using the digital recevier in over...

0 comments posted 19yrs

posted by mottoblatto

0 comments posted 19yrs posted by mottoblatto

Standard PCI Xilinx board with Ethernet port

Hi All, Would anyone please tell me to find a standard PCI FPGA Xilinx board with ethernet port ? Thanks Thuy

1 comments posted 19yrs

posted by thuyp

1 comments posted 19yrs posted by thuyp

verilog genvar, and 2D array access

Hi all, I'm trying to generate 32 16bits registers using verilog generate : reg [15:0] Data_reg [N_REG-1:0]; reg [N_REG...

1 comments posted 19yrs

posted by michel.talon

1 comments posted 19yrs posted by michel.talon

SVF Player

Dear all, We are searching a company having a large Xilinx VIRTEX and/or a large Altera STRATIX for testing our SVF pla...

0 comments posted 19yrs

posted by laurent.gauch

0 comments posted 19yrs posted by laurent.gauch

EDK 9.1i installation

Is EDK9.1i a free upgrade if you have EDK8.1 installed and does anyone know where it can be found. Sven

1 comments posted 19yrs

posted by

1 comments posted 19yrs posted by

Dear Xilinx

Dear Xilinx, I updated my WebPack Saturday night. Thank you for making these available. I have been unable to get my Sp...

3 comments posted 19yrs

posted by dave

3 comments posted 19yrs posted by dave