Latest threads in Field-Programmable Gate Arrays

Another simple DCM question

I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two cl...

3 19yrs

lecroy7200

3 19yrs lecroy7200

ModelSim VHDL Pragmas

Hi All, In one of my VHDL designs I have a section of code that I want different versions for synthesis than for simula...

9 19yrs

ftpeter

9 19yrs ftpeter

EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07

ELECTRONIC DESIGN PROCESSES (EDP) 2007 April 12 & 13, 2007 Monterey Beach Hotel, Monterey, California The Electronic De...

0 19yrs

b_kapoor

0 19yrs b_kapoor

Xilkernel-EDK8.2

Hello, I try to compile an Avnet example (PPC BOOT Loader Design) with my FPGA card. when i build the projet i get the...

2 19yrs

olive_dominguez

2 19yrs olive_dominguez

xilinx ise/edk/modelsim - what does compilation really do?

I have some questions about xilinx ISE/EDK and modelsim simulation. I'm looking for advice/pointers. I'm an reformed so...

2 19yrs

brad

2 19yrs brad

Complex Baseband

Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying...

11 19yrs

saurster

11 19yrs saurster

"undeclared here" error and undesired file persistance in Xilinx Platform Studio

I have a C program I'm developing for the Microblaze SOC processor. I'm using the Xilinx Platform Studio ver. 8.2.02. I...

2 19yrs

tj

2 19yrs tj

RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

Hi, The VHDL standards community needs feedback from VHDL users. Currently the Accellera VHDL TSC is working on enhance...

4 19yrs

jim

4 19yrs jim

Webpack 9.1 Service Pack 3

Hello, did my update go wrong or does also a succeeded update of Xilinx Webpack with 9_1_03i_lin.zip still display "Rel...

4 19yrs

bon

4 19yrs bon

Regarding connecting two Ethernet Mac Phy

Hi everyone, I have an FPGA board with two ethernet MAC interfaces. I want to connect both interfaces in a way that tra...

1 19yrs

madnan.rashid

1 19yrs madnan.rashid

We need avnet fx12 mini module URGENTLY!

Hi all I'm a student of the UAM (University of Madrid, Spain). My TEA (pre thesis) is based on this board. I present it...

0 19yrs

ricardo.ribalda

0 19yrs ricardo.ribalda

Some errors i dont know in XMD

Hi all I am trying running uClinux on MicroBlaze. Memory Test Demo is going all right. In XMD, I download the imagebin...

0 19yrs

sunrui82

0 19yrs sunrui82

Watershed Transform

Is there anyone who has created a VHDL, Verilong or Schematics "WaterShed Transform"?. It is an image transform and I am...

1 19yrs

pbantunez

1 19yrs pbantunez

suggestion for choosing the right FPGA for gigabit transciever

Hi, I need to chose between the Altera Stratix II GX or Stratix III GX and some Xilinx Virtex5 FPGA for an implementati...

5 19yrs

piclist9

5 19yrs piclist9

Problems with Xilinx Parallel III Cable

Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a progr...

20 19yrs

jidan1

20 19yrs jidan1

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays