Field-Programmable Gate Arrays

EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07

ELECTRONIC DESIGN PROCESSES (EDP) 2007 April 12 & 13, 2007 Monterey Beach Hotel, Monterey, California The Electronic De...

0 comments posted 19yrs

posted by b_kapoor

0 comments posted 19yrs posted by b_kapoor

Xilkernel-EDK8.2

Hello, I try to compile an Avnet example (PPC BOOT Loader Design) with my FPGA card. when i build the projet i get the...

2 comments posted 19yrs

posted by olive_dominguez

2 comments posted 19yrs posted by olive_dominguez

xilinx ise/edk/modelsim - what does compilation really do?

I have some questions about xilinx ISE/EDK and modelsim simulation. I'm looking for advice/pointers. I'm an reformed so...

2 comments posted 19yrs

posted by brad

2 comments posted 19yrs posted by brad

Complex Baseband

Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying...

11 comments posted 19yrs

posted by saurster

11 comments posted 19yrs posted by saurster

"undeclared here" error and undesired file persistance in Xilinx Platform Studio

I have a C program I'm developing for the Microblaze SOC processor. I'm using the Xilinx Platform Studio ver. 8.2.02. I...

2 comments posted 19yrs

posted by tj

2 comments posted 19yrs posted by tj

RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

Hi, The VHDL standards community needs feedback from VHDL users. Currently the Accellera VHDL TSC is working on enhance...

4 comments posted 19yrs

posted by jim

4 comments posted 19yrs posted by jim

Webpack 9.1 Service Pack 3

Hello, did my update go wrong or does also a succeeded update of Xilinx Webpack with 9_1_03i_lin.zip still display "Rel...

4 comments posted 19yrs

posted by bon

4 comments posted 19yrs posted by bon

Regarding connecting two Ethernet Mac Phy

Hi everyone, I have an FPGA board with two ethernet MAC interfaces. I want to connect both interfaces in a way that tra...

1 comments posted 19yrs

posted by madnan.rashid

1 comments posted 19yrs posted by madnan.rashid

We need avnet fx12 mini module URGENTLY!

Hi all I'm a student of the UAM (University of Madrid, Spain). My TEA (pre thesis) is based on this board. I present it...

0 comments posted 19yrs

posted by ricardo.ribalda

0 comments posted 19yrs posted by ricardo.ribalda

Some errors i dont know in XMD

Hi all I am trying running uClinux on MicroBlaze. Memory Test Demo is going all right. In XMD, I download the imagebin...

0 comments posted 19yrs

posted by sunrui82

0 comments posted 19yrs posted by sunrui82

Watershed Transform

Is there anyone who has created a VHDL, Verilong or Schematics "WaterShed Transform"?. It is an image transform and I am...

1 comments posted 19yrs

posted by pbantunez

1 comments posted 19yrs posted by pbantunez

suggestion for choosing the right FPGA for gigabit transciever

Hi, I need to chose between the Altera Stratix II GX or Stratix III GX and some Xilinx Virtex5 FPGA for an implementati...

5 comments posted 19yrs

posted by piclist9

5 comments posted 19yrs posted by piclist9

Problems with Xilinx Parallel III Cable

Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a progr...

20 comments posted 19yrs

posted by jidan1

20 comments posted 19yrs posted by jidan1

How is it possible to design a convolutional interleaver with sequential memory writes?

In my interleaver design for FPGA, I am using an external SDRAM for data storage. The clock cycles required to write a...

4 comments posted 19yrs

posted by newsreader

4 comments posted 19yrs posted by newsreader

Compiling simulation libraries of EDK 8.1.02i under Linux

Hello everyone! I try to compile the EDK 8.1.02i simulation libraries with its wizard under Fedora Linux. My problem is...

1 comments posted 19yrs

posted by dtheodor

1 comments posted 19yrs posted by dtheodor