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xilinx ise/edk/modelsim - what does compilation really do?

I have some questions about xilinx ISE/EDK and modelsim simulation. I'm looking for advice/pointers.

I'm an reformed software guy, and my perspective is from using a lot of open source tools like linux and gcc. I've done a lot of linux kernel work so I'm familiar with big project trees, makefiles, etc...

I'm sort of suprised by the state of EDA tools. I've recently spent a little time working with ISE & EDK and trying to get model to simulate a virtex 4.

[To me, it seems like all the tools have their fingers in all the files and things are spread all out and it's *really* difficult sometimes to debug when a flow does not work or modelsim gives you a cryptic messages like "need to recompile blah because foo has been updated".]

I've spent a lot of time with iverilog (icarus) and cver, using gtkwave and makefiles. This is a simple flow which works very reliably. But when I plug the files into ISE I end up with a large tree of who knows what (well, I do know, but you get the point). And when you add modelsim, it just gets worse.

Is there any place (a boot, website,etc...) which describes what happens when I "compile libraries" in ISE or EDK? what get produced? are the files in a standard form? why do they need to be compiled? (I'm guessing that somehow magic private behavior models are secretly passed in a machine readable form to modelsim)

(and why on earth the "workspace" library called "work" on the disk, why not "workspace"? is it just me?)

-brad

Reply to
Brad Parker
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Brad,

Welcome to our world. The short answer is that the software guys that write C compilers and operating systems actually use their software and to some extent understand how others use it, at least as that relates to developing software. The guys who write EDA software have no clue what hardware design is all about for the most part.

As for what compilation does, this is all Modelsim, not Xilinx. I doubt you'll get very far trying to decipher the compiled code unless you want a job at Mentor :)

In my opinion the Modelsim simulator runs remarkably fast considering what has to happen under the hood in your serial execution processor. There is no way an interpreted (as opposed to compiled) simulation engine could keep up with this.

Good Luck, Gabor

Reply to
Gabor

One important difference between VHDL & C (for example) is that "entities", unlike C headers, are referenced in their compiled form, not just copied in as source. So they must have been compiled (strictly, analysed) before any other unit which uses them. There are (with ModelSim) two ways to go about this:

  1. Use vmake - ModelSim's tool which writes a makefile for you, respecting the order of things.
  2. Compile in 2 steps, first compile everything using the -skip ab option (ie skip architectures & bodies), then repeat using the -just ab option (ie just those). That way, all entities (& other stuff) are done before they are needed.

Also, remember that every entity can have more than one architecture: this is as though you could have several implementations of a single C module, all valid together. Of course, the system needs a rule to choose which it shall use. This rule is called "binding".

"work" is the default library name, as defined by VHDL. But it's just that: the default. Use vlib to set up new libraries to your liking, & override the defaults in the vcom command line.

Reply to
David R Brooks

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