I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two clock sources have a fixed phase relationship. I routed a single reset signal to both DCMs. If the DCMs are a 1:1 clock ratio, no problem. However, if they are 2:1 (CLKIN_DIVIDE_BY_2 => TRUE), then often out of reset I see the phase of the output clocks will change. Even though the reset is async, I sync'ed it to each of the DCM's input clocks. This seems to have an effect and does help. The part is a Virtex 4. I have not tried it on any other device.
Any ideas?