Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Places to visit in Amsterdam and Brussells
Hello, I am planning to visit Amsterdam and Brussells in July '08 for a week. What places you would recommend to see for these two cities? Thanks Ashok
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16 years ago
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VHDL document generation utilities
Hi all, I was wondering if there is a good VHDL document generation utility (free or not) out there? I stumbled across an article describing HDLDoc by DualSoft, which seemed promising, but it seems...
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16 years ago
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How to run a block with half the clockspeed on virtex 5
Hi! I have the problem that a core (cordic) can't run with the desired clock (200MHz). As this specific core is totally uncritical for the performance of the system I want to run it with only half of...
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16 years ago
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Serial Transmission w/o 8B/10B encoding
Hi, We have developed a High Speed on FPGA using the MGT/RocketIO to generate high speed signals. Also we receive the high speed signals using the MGT. Due to the nature of the application, we require...
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16 years ago
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How to report LABs' fanout automatically
Hi, I would like to get a fanout report of all utilized LABs in a design in QuartusII. The fitter section of compilation report in QuartusII just only reports fanout of global signal and non-global...
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16 years ago
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new Virtex-5 info
derived from the ISE 10.1 webpack infos V5FXT device-package options VFX70T FF665 FF1136 VFX100T FF1136 FF176 VFX130T FF176 VFX200T FF176 it looks like dual core devices are not offered NEW info for...
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16 years ago
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Timing constraints in ucf
I'm a bit new to FPGA configuration and I couldn't find any messages that addressed my particular problem (although I'm sure this is a common issue). I am using the Xilinx ISE Webpack to configure a...
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16 years ago
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MP7 and Actel Fusion FPGA
Hi! Is there anyone that has made a design for Actels MP7 Arm core on Fusion FPGA? I'am looking for an example project to check my design as it is not functional. I'm just using internal RAM, so it is...
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16 years ago
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EDK9.2 microblaze tutorial
Hi, I tried to use the EDK 9.2 MicroBlaze tutorial in Virtex-4 but at the end of the Base System Builder Wizard I found some problems. I opened the project with Xilinx ISE, imported the new peripheral...
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16 years ago
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why Xilinx doesn't support Dual-Rank DIMM
Hi, I am working on DDR2 memory controller for Dual-rank SODIMM targeting virtex5. I wonder why Xilinx specifies that its MIG2.0 doesn't support DUAL-RANK DIMM? Thank you. Adam
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16 years ago
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Chipscope analyzer GUI problem in Linux
Hi all, I am using Chipscope 9.2i in ubuntu 7.10. Everything works fine except for Chipscope analyzer GUI not showing up. But the weird thing is and are working, I mean the GUI pops up, but analyzer's...
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16 years ago
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Xilinx PLEASE FIX YOUR servers (ISE 10.1)
I can not imagine that the server overload is such a real problem that Xilinx hasnt been able to solve it during the many years of repeated webserver problems. Getting the company website and...
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16 years ago
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AWGN in vhdl
hai..all i am trying to make a particular snr (in dB ) awga (additive white guassian noise.) in vhdl. pls guide me to code it.. i generated the random number using F/F and exor gate, but not getting...
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16 years ago
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BYTE shifter
I wanted to perform a byte shifting of a 24bit vector . the resultant vector is a 48 bit vector . the following is the functinality needed signal BV : std_logic_vector(23 downto 0); signal BYTE_SEL :...
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16 years ago
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using mpmc ddr2 controller with an other processor
hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler leon3 or even picoblaze ; this is for edu. purpose...) ? I...
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16 years ago
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