Latest threads in Field-Programmable Gate Arrays

Writing to DDR RAM on Virtex II Pro Board on PLB Bus

My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus? Background: I am developing a custom IP...

2 18yrs

admbarnett

2 18yrs admbarnett

fpga reset (re-initialize) of spartan3e

Hi, is it possible to force a re initialization from within the fpga ? if I have, for instance. transfered new configur...

3 18yrs

kislo02

3 18yrs kislo02

System Generator Error

Hi, I am trying to generate the ise project files from the system generator token in simulink but i am getting the foll...

0 18yrs

anilcelebi

0 18yrs anilcelebi

Synthesisable Timer in VHDL

hi all: i am currently working on a "toy" design of my first big project (in VHDL) on the Xilinx Spartan III starter ki...

2 18yrs

liubenyuan

2 18yrs liubenyuan

After reset, the PC register of PPC is not back to 0Xfffffffc

Hi, All, I built a PowerPC system on Xilinx ML410 board (Virtex4 fx60), the system contains 64K OCM instruction memory...

2 18yrs

yilu

2 18yrs yilu

Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1

I'd like to announce the release of LogicSim 3.3 and WaveProbe 1.0. LogicSim is an affordable and user-friendly Verilog...

0 18yrs

ngsayjoe

0 18yrs ngsayjoe

ISE 10.1 - Initial experience

I've got a fairly large design that I've been working with in ISE 9.2.04 for a while - it takes about 90% of a V2P100 a...

26 18yrs

ebrombaugh

26 18yrs ebrombaugh

async clk input, clock glitches

Hi FPGA has 1) 50mhz system clock from ext oscillator 2) 4Mhz clk that is async to the 50mhz problem, the 4MHz clk inpu...

62 18yrs

Antti.Lukats

62 18yrs Antti.Lukats

Newbies: Answer to "What is an FPGA?" in video

Hi guys, This is one just for FPGA newbies, and possibly also a place where you can point people when they ask you what...

3 18yrs

tony

3 18yrs tony

FPGA beginner video guide, blog comments by Max Maxfield

Hi all, I announced a Getting Started With Xilinx FPGAs Video Guide here a little while ago. Clive (Max) Maxfield has n...

0 18yrs

tony

0 18yrs tony

Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.

I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled 8.2i on my PC. I also have 9.2i installed on the s...

6 18yrs

dale.prather

6 18yrs dale.prather

Can't read external Flash in a V4 based PPC system through gdb

This is a weird problem. I have a MPMC2 based PPC system with Flash memory attached via opb_emc. The design works fine...

0 18yrs

mbmsv

0 18yrs mbmsv

Webpack 10.1 on 64-bit linux

Congrats to Xilinx on the recent release of ISE 10.1, and thanks for simultaneously releasing WebPack along with ISE Fo...

6 18yrs

jonas

6 18yrs jonas

quick question

what does the following code do output

4 18yrs

FPGA.unknown

4 18yrs FPGA.unknown

ISE 10.1 XST runs in background?

Hi, I installed ISE 10.1 the other day and just tried it out for the first time this morning. I run my synthesis jobs o...

1 18yrs

ebrombaugh

1 18yrs ebrombaugh

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