Hi!
I have the problem that a core (cordic) can't run with the desired clock (200MHz). As this specific core is totally uncritical for the performance of the system I want to run it with only half of the clock (100MHz).
I'm going to use a DCM to divide the clock by 2, and drive the cordic with the halfed clock. I got some problems with hold time violations when going from the lo- speed clock domain to the hi-speed clock domain.
Is there any application note / design example availiable that describes how to do this ?