Field-Programmable Gate Arrays

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Places to visit in Amsterdam and Brussells

Hello, I am planning to visit Amsterdam and Brussells in July '08 for a week. What places you would recommend to see for...
12 comments posted 18yrs
posted by ashok
12 comments posted 18yrs posted by ashok

VHDL document generation utilities

Hi all, I was wondering if there is a good VHDL document generation utility (free or not) out there? I stumbled across...
10 comments posted 18yrs
posted by mbmsv
10 comments posted 18yrs posted by mbmsv

Serial Transmission w/o 8B/10B encoding

Hi, We have developed a High Speed on FPGA using the MGT/RocketIO to generate high speed signals. Also we receive the h...
12 comments posted 18yrs
posted by shakith.fernando
12 comments posted 18yrs posted by shakith.fernando

How to report LABs' fanout automatically

Hi, I would like to get a fanout report of all utilized LABs in a design in QuartusII. The fitter section of compilatio...
0 comments posted 18yrs
posted by RotorLe
0 comments posted 18yrs posted by RotorLe

new Virtex-5 info

derived from the ISE 10.1 webpack infos V5FXT device-package options VFX70T FF665 FF1136 VFX100T FF1136 FF176 VFX130T F...
0 comments posted 18yrs
posted by Antti.Lukats
0 comments posted 18yrs posted by Antti.Lukats

Timing constraints in ucf

I'm a bit new to FPGA configuration and I couldn't find any messages that addressed my particular problem (although I'm...
6 comments posted 18yrs
posted by soxmax_2000
6 comments posted 18yrs posted by soxmax_2000

MP7 and Actel Fusion FPGA

Hi! Is there anyone that has made a design for Actels MP7 Arm core on Fusion FPGA? I'am looking for an example project...
0 comments posted 18yrs
posted by test
0 comments posted 18yrs posted by test

EDK9.2 microblaze tutorial

Hi, I tried to use the EDK 9.2 MicroBlaze tutorial in Virtex-4 but at the end of the Base System Builder Wizard I found...
1 comments posted 18yrs
posted by oscar.odetti
1 comments posted 18yrs posted by oscar.odetti

why Xilinx doesn't support Dual-Rank DIMM

Hi, I am working on DDR2 memory controller for Dual-rank SODIMM targeting virtex5. I wonder why Xilinx specifies that it...
0 comments posted 18yrs
posted by adam0818
0 comments posted 18yrs posted by adam0818

Chipscope analyzer GUI problem in Linux

Hi all, I am using Chipscope 9.2i in ubuntu 7.10. Everything works fine except for Chipscope analyzer GUI not showing u...
1 comments posted 18yrs
posted by wlpstxzhd
1 comments posted 18yrs posted by wlpstxzhd

Xilinx PLEASE FIX YOUR servers (ISE 10.1)

I can not imagine that the server overload is such a real problem that Xilinx hasnt been able to solve it during the ma...
30 comments posted 18yrs
posted by Antti.Lukats
30 comments posted 18yrs posted by Antti.Lukats

AWGN in vhdl

hai..all i am trying to make a particular snr (in dB ) awga (additive white guassian noise.) in vhdl. pls guide me to c...
1 comments posted 18yrs
posted by mvjijuaie
1 comments posted 18yrs posted by mvjijuaie

BYTE shifter

I wanted to perform a byte shifting of a 24bit vector . the resultant vector is a 48 bit vector . the following is the...
2 comments posted 18yrs
posted by nbg2006
2 comments posted 18yrs posted by nbg2006

using mpmc ddr2 controller with an other processor

hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not m...
1 comments posted 18yrs
posted by rponsard
1 comments posted 18yrs posted by rponsard