Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Missing the simplest things - Active HDL - Beginners Questions
Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL. I've started using ActiveHDL(Student Ver), writing some easy VHDL just to get acquainted with both...
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15 years ago
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Still a Beginner: Accumulator has no reset
Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequence of 15 bytes (8 bit signed values = Sample below). I needed to zero the...
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15 years ago
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Xilinx abandoning IEEE-1532 as programming option for iMPACT
Does anyone know if this is true or not? All our programming files are based on IEEE-1532 Dave
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15 years ago
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Standard forms for Karnaugh maps?
Is there a 'normal' way to write down K-maps with more than 4 inputs? I've just written some code to verify logic which implements n-input K-maps. The user has to initialise a square or rectangular...
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15 years ago
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Hot mangas$B!'(BNaruto 406, One Piece 505, Bleach 328
Hot mangas$B!'(BNaruto 406, One Piece 505, Bleach 328 The hottest mangas and the latest chapters Manga news, Most popular mangas, Latest mangas, Latest chapters A New Wonderful Manga: Maken-ki! Hi,...
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15 years ago
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Re: claws-mail password recovery
*Ihan kiva ja asiantunteva firmarypästiedote lopussa! ______________________________________ [Heikki Jaakkola, Energia, 02.06.2008] Lisää aurinkosähköä samalla rahallaAurinkosähkön suuri...
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15 years ago
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NVRAM design in CPLD
Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in my curent CPLD design, occasionally I need change the content inside, instead of...
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15 years ago
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synthesis error
Hi, synthesizing the following code yields an error. CODE : ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:22:54...
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15 years ago
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System Generator Xilinx ML403
Is it possible to use the System Generator for DSP with the ML403 with GigabitEthernet or USB? They only support ML402 directly, why? Has anybody a BSB and sources how to manage it to use ML403 for...
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15 years ago
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How to start DMA from user_logic.vhdl (hardware side)
Hi, is it possible to configure and start the Xilinx IPIF dma s/g transfer via the userlogic. how can i write into the dma registers from vhdl? thnx sebastian
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15 years ago
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mapping error
Hi all; i am trying to use lock_pins to lock theinstantiated LUTs pins , iam using ISE 9.1 and my family is virtex 2 pro, first i tried to do this using ucf file and it works, but i want to do this by...
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15 years ago
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SYSACE problems on ML402 (virtex 4)
Hi all, I'm working on a self reconfigurating system on ml402 (a virtex 4 sx35 device). I tested all bitstreams, full and partial, and they work fine. The problems come when I try to make a self...
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15 years ago
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Xilinx register inits
Hi, I have a problem with getting the correct startup values for an array of bytes on a Xilinx V5 When the array is declared it is initialised using a function (which of course has only constant...
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15 years ago
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Hardware Demonstration Platform
Hi all, Im working on trimode Ethernet Mac core on Virtex 4. There is a tool in thie core called ":Xilinx Hardware Demonstration Platform" which acually displays the peckects being send and you can...
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15 years ago
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FPGA area use by module?
Hi! I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since it was too full. Now I have to optimize or reduce some modules to win some area,...
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15 years ago
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