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FPGA area use by module?

Hi!

I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since it was too full. Now I have to optimize or reduce some modules to win some area, but I can only guess which ones use a lot of area so optimizing them would win me significant = space.

Is there a tool (or am I overlooking something in ISE) which tells me whi= ch part of the design uses how much space? I'm aware that optimizing across hierarchy may make this information inaccurate, but still I guess it woul= d show me the right way...

- Philip

--=20 Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist man als Triebt=E4ter stundenlang ziellos durch's Parkhaus geirrt. (Andreas Leidig)

Reply to
Philip Herzog
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I never found one. I have built each module seperately to get an idea of how big they are. I just drop the module into the largest package device of the family, and check carefully that it doesn't all get optimized away.

G.

Reply to
ghelbig

Many tools flatten the netlist before P&R so they don't know by then which module anything came from.

You can try routing individual modules to see how big they are (even though it won't run that way). It should be a rough approximation to the size, but won't be exact. It will work better if you specify a smaller device so that P&R has some work to do. It should report LUTs used, use that for area.

-- glen

Reply to
glen herrmannsfeldt

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I believe ISE 10.1 has a hierarchical report of each module consumption. It is quite detailed and lists the resource types and for a number of levels of hierarchy. Maybe try updgrade ISE to 10.1?

Reply to
John McGrath

Philip Herzog schrieb:

Hi Philip, if you just want to get an idea about the area of each module, you can use the floorplanner tool. Make sure that "keep hierarchy" is enabled in your synthesis properties, so each module will be shown in a different colour. If the PAR doesn't finish the routing, disable it. Placement only is all you need to see the area in floorplaner.

have a nice synthesis Eilert

Reply to
backhus

space.

You can also have a look at the modules in floorplanner just after translate (again, the "keep hierarchy" is essential). This is the size of the modules after synthesis, but the map stage may increase or decrease the size of the design by optimising or duplicating logic.

Rob

Reply to
Rob

Philip Herzog ha escrito:

This is a good free 3rd party tool for this purpose:

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Regards, Marc

Reply to
jetmarc

You can also try ADEPT, which also extracts hierarchical logical utilization and lots more...

ADEPT:

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Screenshot:
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It also exports the view to Excel spreadsheet: e.g
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Cheers, Jim

Reply to
Jim Wu

You beat me to it :) Thanks for the kind words BTW!

While I'm here, I've been hacking on this tool lately to get things like arrays of LUTs with similar names merged into a single entry so that the details of what's being used up within your lowest level blocks is visible.

Watch this space...

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply to
Martin Thompson

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Any module that has been put in an area group will have its own resource utilization reported in the area groups section of the map report.

For all of the cores that we have designed for our EDK package, we create core level UCF files and put the core in an area group. Some times we put constraints on the area group, and some times it is just there to get more detailed reporting.

Refer to the Xilinx constraint guide for more information on area group constraints.

Regards,

John McCaskill

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Reply to
John McCaskill

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