I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since it was too full. Now I have to optimize or reduce some modules to win some area, but I can only guess which ones use a lot of area so optimizing them would win me significant = space.
Is there a tool (or am I overlooking something in ISE) which tells me whi= ch part of the design uses how much space? I'm aware that optimizing across hierarchy may make this information inaccurate, but still I guess it woul= d show me the right way...
--=20 Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist man als Triebt=E4ter stundenlang ziellos durch's Parkhaus geirrt. (Andreas Leidig)