Latest threads in Field-Programmable Gate Arrays

Missing the simplest things - Active HDL - Beginners Questions

Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL. I've started usin...

1 18yrs

jflan

1 18yrs jflan

Still a Beginner: Accumulator has no reset

Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequ...

3 18yrs

meralonurlu

3 18yrs meralonurlu

Xilinx abandoning IEEE-1532 as programming option for iMPACT

Does anyone know if this is true or not? All our programming files are based on IEEE-1532 Dave

0 18yrs

dscolson

0 18yrs dscolson

Standard forms for Karnaugh maps?

Is there a 'normal' way to write down K-maps with more than 4 inputs? I've just written some code to verify logic which...

13 18yrs

nospam

13 18yrs nospam

Hot mangas$B!'(BNaruto 406, One Piece 505, Bleach 328

Hot mangas$B!'(BNaruto 406, One Piece 505, Bleach 328 The hottest mangas and the latest chapters Manga news, Most pop...

0 18yrs

mangaboy001

0 18yrs mangaboy001

Re: claws-mail password recovery

*Ihan kiva ja asiantunteva firmarypästiedote lopussa! ______________________________________ [Heikki Jaakkola, Energia,...

0 18yrs

christian.rissanen

0 18yrs christian.rissanen

NVRAM design in CPLD

Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in...

3 18yrs

heavenfish

3 18yrs heavenfish

synthesis error

Hi, synthesizing the following code yields an error. CODE : -----------------------------------------------------------...

4 18yrs

webmaster

4 18yrs webmaster

System Generator Xilinx ML403

Is it possible to use the System Generator for DSP with the ML403 with GigabitEthernet or USB? They only support ML402...

0 18yrs

erixx

0 18yrs erixx

How to start DMA from user_logic.vhdl (hardware side)

Hi, is it possible to configure and start the Xilinx IPIF dma s/g transfer via the userlogic. how can i write into the d...

0 18yrs

fatfpga

0 18yrs fatfpga

mapping error

Hi all; i am trying to use lock_pins to lock theinstantiated LUTs pins , iam using ISE 9.1 and my family is virtex 2 pr...

3 18yrs

fatma.abouelella

3 18yrs fatma.abouelella

SYSACE problems on ML402 (virtex 4)

Hi all, I'm working on a self reconfigurating system on ml402 (a virtex 4 sx35 device). I tested all bitstreams, full a...

0 18yrs

paolo.furia

0 18yrs paolo.furia

Xilinx register inits

Hi, I have a problem with getting the correct startup values for an array of bytes on a Xilinx V5 When the array is dec...

8 18yrs

BertyBooster

8 18yrs BertyBooster

Hardware Demonstration Platform

Hi all, Im working on trimode Ethernet Mac core on Virtex 4. There is a tool in thie core called ":Xilinx Hardware Demo...

0 18yrs

amboafridi

0 18yrs amboafridi

FPGA area use by module?

Hi! I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since...

9 18yrs

phu

9 18yrs phu

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