Field-Programmable Gate Arrays

Xilinx abandoning IEEE-1532 as programming option for iMPACT

Does anyone know if this is true or not? All our programming files are based on IEEE-1532 Dave

0 comments posted 18yrs

posted by dscolson

0 comments posted 18yrs posted by dscolson

Standard forms for Karnaugh maps?

Is there a 'normal' way to write down K-maps with more than 4 inputs? I've just written some code to verify logic which...

13 comments posted 18yrs

posted by nospam

13 comments posted 18yrs posted by nospam

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Hot mangas$B!'(BNaruto 406, One Piece 505, Bleach 328 The hottest mangas and the latest chapters Manga news, Most pop...

0 comments posted 18yrs

posted by mangaboy001

0 comments posted 18yrs posted by mangaboy001

Re: claws-mail password recovery

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0 comments posted 18yrs

posted by christian.rissanen

0 comments posted 18yrs posted by christian.rissanen

NVRAM design in CPLD

Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in...

3 comments posted 18yrs

posted by heavenfish

3 comments posted 18yrs posted by heavenfish

synthesis error

Hi, synthesizing the following code yields an error. CODE : -----------------------------------------------------------...

4 comments posted 18yrs

posted by webmaster

4 comments posted 18yrs posted by webmaster

System Generator Xilinx ML403

Is it possible to use the System Generator for DSP with the ML403 with GigabitEthernet or USB? They only support ML402...

0 comments posted 18yrs

posted by erixx

0 comments posted 18yrs posted by erixx

How to start DMA from user_logic.vhdl (hardware side)

Hi, is it possible to configure and start the Xilinx IPIF dma s/g transfer via the userlogic. how can i write into the d...

0 comments posted 18yrs

posted by fatfpga

0 comments posted 18yrs posted by fatfpga

mapping error

Hi all; i am trying to use lock_pins to lock theinstantiated LUTs pins , iam using ISE 9.1 and my family is virtex 2 pr...

3 comments posted 18yrs

posted by fatma.abouelella

3 comments posted 18yrs posted by fatma.abouelella

SYSACE problems on ML402 (virtex 4)

Hi all, I'm working on a self reconfigurating system on ml402 (a virtex 4 sx35 device). I tested all bitstreams, full a...

0 comments posted 18yrs

posted by paolo.furia

0 comments posted 18yrs posted by paolo.furia

Xilinx register inits

Hi, I have a problem with getting the correct startup values for an array of bytes on a Xilinx V5 When the array is dec...

8 comments posted 18yrs

posted by BertyBooster

8 comments posted 18yrs posted by BertyBooster

Hardware Demonstration Platform

Hi all, Im working on trimode Ethernet Mac core on Virtex 4. There is a tool in thie core called ":Xilinx Hardware Demo...

0 comments posted 18yrs

posted by amboafridi

0 comments posted 18yrs posted by amboafridi

FPGA area use by module?

Hi! I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since...

9 comments posted 18yrs

posted by phu

9 comments posted 18yrs posted by phu

RAM and shift register constraints

hi all; I am using HWICAP to configure certain LUTs , and as mentioned in the HWICAP data sheet that "when LUTs are con...

4 comments posted 18yrs

posted by fatma.abouelella

4 comments posted 18yrs posted by fatma.abouelella

Xilinx tools in Windows or Linux - Suggestions

Friends, I have been using the Xilinx tools ISE, EDK in Windows environment. But now planning to use Linux PC for runni...

5 comments posted 18yrs

posted by muthusnv

5 comments posted 18yrs posted by muthusnv