NVRAM design in CPLD

Hi all,

For the ram implied in a CPLD design, will the data written in it remain after power off?

I have a small rom in my curent CPLD design, occasionally I need change the content inside, instead of reprogramming it, I want something like a nvram that I can update through the uP dynamicallly.

Thanks, Jay

Reply to
jay
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That depends on the CPLD. Some do have a mode, where you can load the CPLD config latches and not the NV_Fuse_memory. (I think Atmel ATF15xxBE series have the twin modes)

not sure of the details, ie when the change-over occurs and what the pins do during re-load

-jg

Reply to
Jim Granville

Thanks, but I'm only using a general CPLD from A.

Jay

Reply to
jay

If you can't switch the CPLD for another PLD, I'm afraid you'll have to reprogram the device as a whole to do this. If you are open to change though, in Lattice XP2 FPGA (which are flash based -so system- wise they're very close to big CPLDs) there is a relatively small flash memory (TAG memory) with an external (and internal) SPI interface. The TAG memory can be reprogrammed while these device are operating. Alex

Reply to
Alex

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