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Missing the simplest things - Active HDL - Beginners Questions

Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL.

I've started using ActiveHDL(Student Ver), writing some easy VHDL just to get acquainted with both VHDL and the Aldec tool. What I don't understand is the integrated implementation portion. If I were to want to do a Altera design, for example, do I need to have the Altera toolset installed in order to build the jedec file or does the Aldec tool do that also? I guess I am at a loss at the point between designing/simulating the project and implementation with ActiveHDL.

Help me see the light. Thanks, Jim

Reply to
Jim Flanagan
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You still need a separate tool to do the synthesis, whether it's Synplicity or ISE or Quartus. Then, you still need ISE or Quartus even if you used Synplicity for the synthesis, to do the final place and route, and build the file to download into the FPGA (bit or pof file). Aldec will only do simulations, but it does allow you to launch these other tools from within its GUI. You don't have to, though, you could launch them yourself if you find Aldec's design flow confusing.

Dave

Reply to
Dave

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