Why no depletion mode LDOs?

No limitations. You just have to hold or limit the gate at a certain level and not let it snap to the rail. BTDT, it ain't particularly difficult.

PNP or PMOS is the usual structure for LDOs, with the usual stability issues.

No, it acts as a current-limiting source follower. If the gate voltage starts at zero, the output voltage will be fairly low. It's not much different from an enhancement fet in startup: the gate drive determines what happens.

They would be useful as series pass elements, if they were more commonly available.

You have proudly announced, many times, how you have killfiled me and any followups to my posts. And, as many times, you can't stand to not snoop. That makes you the weenie, not to mention asshole, here.

Or maybe you're getting senile dementia. That damages near-term memory. Yeah, that's consistant with your telling old stories and not saying much about anything new.

Why don't you post your .asc (LTspice schematic) file for all to evaluate for stability? ...Jim Thompson

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Sounds like HMOS -- IIRC, the 8088 was among them, essentially regular NMOS circuitry, except the drain load resistor (which is a diffusion anyway and subject to nonlinear MOS effects, if used as such) was constructed a bit differently, and doped / implanted enough to make it behave as a saturated (that is, current saturation region) NMOS transistor, a crude CCS.

Tim

-- Deep Friar: a very philosophical monk. Website:

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

I just found out that the SPICE models have their limits. Normally a BSP149 can't sink an 11 amp spikeroo into a capacitor. But on the simulator it does.

Noooo, noooo, say it ain't so!

Normally a

It can sink 2 amps with about +1.2 on the gate, and the graph quits there. It might get close to 11 if you put a lot of volts on the drain and the gate. Even depletion fets (including jfets, mesfets, phemts) enhance.

One problem with using a depletion fet in an LDO is that you can't fully turn it off (without a negative gate supply, anyhow) so the output will rise to Vpinchoff at light loads.

But Spice models are often wrong in the far corners of the part envelope.

Truth hurts, doesn't it?

Did you test that hypothesis?

I've had a circuit work whenever a scope probe was attached. I was tempted to ship one with every box. ;-)

On a sunny day (Wed, 09 May 2012 12:18:19 -0700) it happened John Larkin wrote in :

OK, thanks, I see.

I have often wanted to order some, but forgot every time, I think I need to play with some to get some better idea of the 'current limiting'. Will be on the next order.

I've been there before! I've found that a FET probe will usually allow me to get to the bottom of it.

Ok, I say it: It ain't so!

It was driver error, in the guy in front of the computation machine. I had forgotten about the Cgd capacitances which does not miraculously become zero in depletion mode devices. Whew ...

Ok, that I knew but I didn't imagine they could enhanced this much.

Got to be careful. One some of these there is more than one model. But full turn-off is not problem unless youare operating with extremely low voltages, mostly less than 3V. And then you'd have problems with almost any FET.

series

Junction fets are limited in enhancement by the gate diode turning on. So jfets don't enhance much because +0.6 volts is a small fraction of the pinchoff voltage. PHEMTS, with low pinchoff voltages (like, -0.5 for some) can enhance to values like 2x Idss with a little forward gate bias. That can be useful.

I was playing with one PHEMT and thought I saw something weird happen as the gate began to conduct, maybe some sort of bipolar or unijunction mode or something. Didn't have time to explore. Imagine a Pseudomorphic Heterojunction Unijunction Transistor. That would be pronounced, of course, "phut".

Joerg already has the acronym "phut" copyrighted :-) ...Jim Thompson

series

This one (BSP149) is listed with 140mA min at Vgs=0 and the datasheet says the current won't go past 630mA or so even at Vgs>10V. But it sure does in cyberspace, simulator says 11 amps. So it looks like this wasn't really pilot error on my side. Figure 2:

Did it morph? :-)

Sometimes not-so-far corners. I've made a habit, when using a new model, of doing a simulated curve trace, and comparing it to datasheet data, and, if possible a real curve trace.

I've been amazed by some of the departures from reality in manufacturers' "own" models (which frequently appear to be outsourced).

The problem is that the discrete part manufacturers don't provide "corner" models. But the ASIC processing houses do. It is not unusual for me to have to simulate 45 (or more) "corners" when validating the final design of an ASIC.

That's a good idea.

Just the opposite is the problem. Mostly in-house "slugs" get assigned the task of modeling. A famous un-named "analog" house won't even pay a moderate price for an accurate model of their op-amps. ...Jim Thompson

Is that Harley Heinrich's outfit?

Cheers

Phil Hobbs