1. Home
  2. Electronics Design
  3. LDO

LDO

I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was easier to just do it from available parts than find a new regulator to buy. Loop comp is the first wild guess, but it looks fine. At 0.3 volts drain-source, the mosfet is acting like a variable resistor.

Version 4 SHEET 1 1080 680 WIRE -48 -32 -144 -32 WIRE 336 -32 256 -32 WIRE 512 -32 336 -32 WIRE -144 -16 -144 -32 WIRE -48 0 -48 -32 WIRE 512 16 512 -32 WIRE -240 128 -272 128 WIRE -112 128 -176 128 WIRE 0 128 -32 128 WIRE 256 128 256 -32 WIRE 512 128 512 96 WIRE -144 176 -144 64 WIRE -432 192 -464 192 WIRE -384 192 -432 192 WIRE -272 192 -272 128 WIRE -272 192 -304 192 WIRE -176 192 -272 192 WIRE 0 208 0 128 WIRE 0 208 -112 208 WIRE 48 208 0 208 WIRE 208 208 128 208 WIRE -176 224 -272 224 WIRE -432 272 -464 272 WIRE -384 272 -432 272 WIRE -272 272 -272 224 WIRE -272 272 -304 272 WIRE 256 288 256 224 WIRE 400 288 256 288 WIRE 448 288 400 288 WIRE 496 288 448 288 WIRE 656 288 576 288 WIRE 800 288 656 288 WIRE 848 288 800 288 WIRE 880 288 848 288 WIRE -272 304 -272 272 WIRE -144 304 -144 240 WIRE 656 320 656 288 WIRE 448 336 448 288 WIRE 800 336 800 288 WIRE -272 448 -272 384 WIRE 448 464 448 400 WIRE 656 464 656 400 WIRE 800 464 800 416 FLAG 448 464 0 FLAG 400 288 OUT FLAG 512 128 0 FLAG -48 0 0 FLAG -432 192 OUT FLAG -272 448 0 FLAG 800 464 0 FLAG 656 464 0 FLAG 848 288 LOAD FLAG -144 304 0 FLAG 336 -32 1.8 FLAG -432 272 1.8 SYMBOL cap 432 336 R0 WINDOW 0 -77 13 Left 2 WINDOW 3 -79 45 Left 2 SYMATTR InstName C2

SYMBOL voltage 512 0 R0 WINDOW 0 56 41 Left 2 WINDOW 3 54 80 Left 2 SYMATTR InstName V1 SYMATTR Value 1.8 SYMBOL Opamps\\UniversalOpamp2 -144 208 R0 WINDOW 0 73 45 Left 2 SYMATTR InstName U1 SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg SYMBOL res 144 192 R90 WINDOW 0 76 52 VBottom 2 WINDOW 3 84 52 VTop 2 SYMATTR InstName R2 SYMATTR Value 22 SYMBOL voltage -144 80 R180 WINDOW 0 55 81 Left 2 WINDOW 3 56 50 Left 2 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res -288 176 R90 WINDOW 0 -51 51 VBottom 2 WINDOW 3 -43 53 VTop 2 SYMATTR InstName R3 SYMATTR Value 1K SYMBOL cap -176 112 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL res -16 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL current 800 336 R0 WINDOW 3 -175 -104 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 0.3 300m 0 0 100m) SYMATTR InstName I2 SYMBOL res 480 304 R270 WINDOW 0 82 55 VTop 2 WINDOW 3 73 55 VBottom 2 SYMATTR InstName R6 SYMATTR Value 1m SYMBOL nmos 208 128 R0 WINDOW 0 124 30 Left 2 WINDOW 3 85 72 Left 2 SYMATTR InstName M1 SYMATTR Value NTLMS4504N SYMBOL res 640 304 R0 WINDOW 0 -63 62 Left 2 WINDOW 3 -59 97 Left 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res -288 288 R0 WINDOW 0 52 74 Left 2 WINDOW 3 51 107 Left 2 SYMATTR InstName R4 SYMATTR Value 5K SYMBOL res -288 256 R90 WINDOW 0 70 62 VBottom 2 WINDOW 3 76 63 VTop 2 SYMATTR InstName R7 SYMATTR Value 1K TEXT 696 112 Left 2 !.tran 500m uic TEXT 696 0 Left 2 ;1.8 to 1.5 LDO TEXT 688 48 Left 2 ;JL Oct 11, 2016 TEXT 104 72 Left 2 ;IRLM6344 TEXT 120 112 Left 2 ;SOT23 TEXT -96 288 Left 2 ;NCS2005 TEXT -96 320 Left 2 ;SOT23 TEXT 344 416 Left 2 ;1206

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin
Loading thread data ...

Hello John,

I love simulations. What would make me a little bit nervous is the small oscillation at ~235kHz. Doubling the output C silences it but I tried to add small C's here and there and it only got worse. Not even the frequency changes notably. So I wonder what determines the frequency? The rise time of the OpAmp? A better idea how to silence it anyone?

Cheers

Robert

Reply to
Robert Loos

SNIPPED

Novice query here.

Why is there no DC feedback path around the op amp?

If I short circuit C3 it appears to still work the same.

Reply to
doggerel

There is: The signal OUT.

--

-TV
Reply to
Tauno Voipio

The feedback is from OUT, which is the thing we are ultimately trying to control.

Yes, but the step-load regulation isn't as good.

Currently is a P+I (proportional + integral) control loop, which has essentially zero DC error. Without the cap, it's a proportional-only loop with a finite error. Having the RC in the feedback path gives more knobs to turn too. The values were guessed, so probably need more scientific tuning.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

I don't see an oscillation in my sim. Maybe you have different Spice settings; LT spice is a speed demon and it can be quirky.

It will oscillate in my sim if R5 is doubled, which is cutting things close. But then a tiny bit of added ESR in C2 fixes it again.

The transient load regulation is super good, so the loop is needlessly hot. 1 uF and 20K is more prudent, and those values are already on the BOM.

The DDR3 ram will probably pull current in short bursts, as CPU cache is topped off. The 47uF ceramic cap helps; I could put two of them on the board for luck.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Is there something novel here? I'm missing it.

Reply to
bloggs.fredbloggs.fred

Just a 0.3 volt LDO, using a mosfet in ohmic mode.

Why don't you post a more interesting circuit?

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Don't have time to put this on LT Spice, but do an AC analysis of the input and output impedances when it's running at design current and maybe

2x and 1/2 as much. Look for where the real part goes negative, and consider whether that's going to find fertile ground for oscillation.

(If you've got power gain and more than 180 degrees of phase shift, you're pretty much guaranteed that the output impedance will go negative at some frequency.)

To sweep for an impedance shove a voltage or current source in there someplace (or use an existing one). Set the DC value to zero (or use what you had been for your simulation), set the AC value to 1, run the sweep, and plot the current or voltage vs. frequency. The admittance (or impedance) jumps right out at you.

--
www.wescottdesign.com
Reply to
Tim Wescott

The transfer curve of the fet is very nonlinear, and it's acting like a variable resistor, so the output time constant is continuously changing. I wouldn't want to try to write closed-form equations for the load-step response, or to evaluate stability over the load range. This is clearly a case where Spice wins.

The loop is unnecessarily hot, but was a first guess. It needs tweaking. What's important is to design a circuit that can be tweaked.

The LDO is powering a 4 gbit DDR3 ram and the FPGA bank that interfaces it. I have no good estimate of either the active or the idle current, or the time profile of the load current. The big output cap helps a lot here. I may need a dump resistor (R1) but probably not; gotta research the FPGA and the dram to be sure. The output can't go up much, given there's only 1.8 volts available.

Simulated load steps are a great way to estimate, well, load step response. Ringing suggests low phase margins.

Load steps do that, in the time domain. But they account for the large nonlinearities, which AC analysis doesn't.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

You've reminded me again of what I would have made my main line of research, had I been able to get it piled higher and deeper.

Basically, the world needs an extension of Lyapunov's 2nd method for determining stability that doesn't require a bunch of messing around solving nasty nonlinear differential equations, but that does cough up answers that are as intuitive as a resonant circuit's Q, or a phase margin on a Bode plot.

Dunno if you remember it, but Lyapunov's 2nd method is a way of determining if a nonlinear system is stable, and, to some extent, how fast it'll settle. It involves cooking up a cost function that's analogous to the total system energy, then proving that the system always moves to a lower cost state. I see no reason that it can't be done numerically, allowing one to basically say "is this system globally stable" and having something like LT Spice say "yes" or "no". Having it cough up something analogous to a measure of Q in a resonant circuit would be a plus, so you know if it's on the verge of breaking into song.

--
www.wescottdesign.com
Reply to
Tim Wescott

I get the same oscillation. It gets a lot worse when the load kicks in at 300ms

If one add a feedback capacitor from the opamp output to the inverting input of 100pF, the oscillation disappears completely. That's the normal way to compensate an LDO, at least how I normally do it :-)

Cheers

Klaus

Reply to
klaus.kragelund

Just use a TLV431 with the NMOS... why make it complicated? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

                          In Memoriam... 
                       James Ralph Thompson 
                October 12, 1918 - November 7, 2008
Reply to
Jim Thompson

Post the sim and I'll consider it. But we don't stock the LTV, and I'd rather use parts that we have.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

My sim doesn't oscillate, but there's not much safety margin.

It looks good with a tweak to the feedback RC: 50K + 1 uF. As I said, the initial loop comp was a wild guess.

Giant ceramic caps have become affordable, things like 47u or 100u,

6.3 volts, 1206, so lots of output cap removes responsibility from the control loop. 
--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

I also need to predict load step overshoot and undershoot, and pick part values, so may as well Spice and fiddle until it looks good. "It looks good" isn't a quantified error function.

It's shocking how much electronics I design versus how little serious math I use. But I don't do long division with a quill pen on parchment any more either. Seems to me that a good grounding in the theory eventually transfers into fairly quantitative instincts, which becomes the basis for simulation.

I know a guy who got a PhD in control theory, and it was really hairy. Not bode plot stuff any more.

The mosfet might burst into RF oscillation too, but I'm guessing it's unlikely with it acting like a resistor. But the gate resistor is good insurance.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

OK, I overlooked the 'out' net, I can see that as the P feedback and also the I fb via the RC network.

Thanks for the explanation its appreciated.

Reply to
doggerel

Thanks Tauno, I missed that, pretty obvious in hindsight!

Reply to
doggerel

For anything other than messing with the included LTSpice switcher models, I believe it's best to have "alternate solver" selected for accurate results.

Reply to
bitrex

Am 12.10.2016 um 23:35 schrieb snipped-for-privacy@gmail.com:

Yes, it is silent then. Reducing the value of R5 also does the job. I'd like to mention that the load 'step' in this simulation is _very_ soft (it takes 10ms to linearly rise the current). DDR RAM would be much faster. If I specify a rise and fall time of 10ns you can see the step in the output and further reduction of R5 becomes necessary. I've set R5=33k and C3=100p and it's ok. With R5=50k it is only silent until the load comes in.

Cheers

Robert

Reply to
Robert Loos

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.