Biasing this FET -- how does the bias work??

In every schematic on that data sheet, it seems that there is a DC path to ground (either a resistor, an inductor, or a series combination). That means that the bias voltage is zero in all these cases.

** Groper alert !

** The particular GASFET operates with normal ( ie 140mA) drain current with no gate bias.

The data says that in 3 places while a negative gate voltage of about 1.5 volts will reduce the drain current to zero

Many JFETS are similar.

...... Phil

Thanks John, but since the bias voltage is, as you say, zero volts at the gate, then how can it function as a Class A small signal linear amplifier? I would think it could only function as a Class C amp...?

Thanks Again,

Bill

John P> > I know how to bias FETS, but how this particular Class A linear

"billcalley"

** WAKE UP !!

It is NOT a mosfet !!

The gate does not need to be biased for the device to conduct.

...... Phil

Thanks for the feedback Phil. I understand what you are saying, but since WJ "recommends" that this part never go positive at the gate, how can an input signal have the appropriate voltage swing (head room) it needs for linear operation (since it is biased at zero volts, but can only swing negative)?

Thanks,

Bill

Phil Allis>

Is your FET-biasing knowledge limited to enhancement-mode MOSFETs?

Right, John. Bill, it's a depletion-mode FET; giveaways are the Idss and negative Vp specs: Pinch-off Voltage, Vp = -1.5V typical.

--
 Thanks,
    - Win

** STOP BLOODY TOP POSTING !!!!!!!!!!!!

** Where ????

...... Phil

This particular fet passes about 140 mA when its gate to source voltage is zero and its drain to source voltage is 5 volts. Once biased that way, the drain current increases when the gate voltage goes incrementally positive, and decreases when the gate voltage goes incrementally negative. This is very ordinary biasing for a jfet.

If the gate to source voltage goes negative to somewhere between -1.5 and -3, the drain current cuts off (falls below .6 mA). At some rather small positive gate to source voltage, the gate diode becomes forward biased and is no longer insulated from conducting current into the channel. Normal signal swing positive peaks stay below this voltage.

See:

Thanks John and Win -- now it becomes clear! And John's link really opened-up my eyes on how MESFET devices work.

Best Regards,

Bill

John P> > Thanks John, but since the bias voltage is, as you say, zero volts at

I thought you knew about biasing FETs? This is an N-channel FET not a MOSFET. And an N channel FET draws maximum bias when Vgs = 0V.

Meindert

Calm down Phil, this is electronics BASICS.

That's not an accurate statement as it stands. If you said, it's not an enhancement-mode mosfet, that'd be correct. A depletion-mode mosfet works exactly the same as Bill's FH101 GaAs MesFet: full conduction at zero volts, and requiring a negative gate voltage to turn off, yet it's still a mosfet. An example of a depletion-mode mosfet is my favorite Supertex LND150,

which has myriad uses, some of which I've detailed on s.e.d.

My summer students just made a cool two-terminal, self-powered current regulator using an LND150. This floating current-source / current-sink operates from 1 - 250mA, with a compliance range of 6 - 500V. It has a current-pulse feature, that's especially useful for high-voltage power-supply testing, such as for piezo amplifiers; tube-amplifier aficionados, take note. Yep, just one more example of why I recommend the LND150 (TO-92 package) and its SMD mate, the LND250. Supertex' DN2540N5, in a TO-220 power package, is a useful 400V 150mA depletion-mode mosfet.

--
 Thanks,
    - Win

"Winfield Hill"

** But it is perfectly correct in CONTEXT.

ALL that any comment EVER has to be.

..... Phil

Most MOSFETs *are* N-channel fets. The rest are P-channel fets. And most MOSFETS have Idss=0.

It's actually a mesfet, a metal-gate GaAs fet. It draws a considerable drain current Idss at Vg=0. Negative gate voltage reduces Id until pinchoff, at about -1.5 on the gate. Positive gate voltage will enhance it, up to the point that the gate starts to conduct, with enhanced Id of about 1.5 Idss typical. PHEMTS enhance better, roughly

2x Idss.

John

Yabbut, you probably won't have much luck using gate-leak bias. ;-)

Cheers! Rich

--
So what?

It sounds like you\'re trying to make yourself look like an expert
who can relate vacuum tube grid leak bias to MOSFET gate current.

It won\'t work, and you don\'t even know why.

I know why there's no gate-leak bias - it was a joke, hence the smiley. Maybe you've never heard of "grid-leak bias"?

Thanks, Rich