Unfortunately, the fastest flipflops that you can buy don't have set and reset inputs. All you get is differential clock, data in, and data out. They are intended to be data resynchronizers. So you'll probably have to make an RS flop out of gates, which will slow things down a bit.
There is. We see it on a scope, and increasing the base resistor fixes it.
JT said that it's caused by the gain/phase of the opamp loop, but he won't explain it past that silly hand-waving.
Old people with bad joints need to be careful about too much hand waving.
It's too complex for you to understand, but Gerhard Hoffmann did.
John Larkin just can't resist trying to be an asshole.
I wonder if his products reflect that ?:-) ...Jim Thompson
if purely for the heck of it an FPGA maybe, use two LVDS inputs as comparators, use enable on output pin to simulate open collector
-Lasse
The current source that we recently fixed is the one I posted about in the "follies" thread. It's on a product. Details in that thread.
FPGA 555! What a concept. You might hit 100 MHz with that.
On the FPGAs that we've tried, the LVDS inputs do behave like pretty good r-r comparators.
Do you mean a drop-in replacement, with all the same levels? That would take a bunch of ICs on a PC board. Seems like a silly thing to do. Get JT to design that as an IC.
Seems a bit redundant. Hans Camenzind's book
includes a more modern design for the 555. Jim Thompson might be able to do better - the book was published in 2005 and Hans Camenzind would have completed his revised design earlier than that, and process technology has moved on since then - but it would be a waste of money. Putting the timer in the same package as a highish-current output switch made sense in 1971, but it stopped being a sensible way of partitioning most circuits in the early 1980's.
-- Bill sloman, Nijmegen
yeh something like that, I just tried writing the 10 lines I think it takes and synthesing in a spartan6 around 11ns from input to output
I've seen several examples of using as the comparator to make a delta sigma ADC in an FPGA
actually think someone has a patent on doing it
-Lasse
Already have, as a custom... tweakable 100MHz clock, PVT stabilized :-) ...Jim Thompson
Well, they're not that good. They apparently have complementary n-channel and p-channel diff pairs, like a r-r opamp does, so the offset shifts at some common-mode voltage as the pairs swap over. The error can be 10s of millivolts, so you'd get a mediocre ADC.
The problem is poorly defined.
You said "which means adhering to its pinout descriptions" which may or may not include electrical levels.
Write a firm specification and I'll consider it.
You are aware of how a feedback based control loop operates, right?
Can you not envision an inherent oscillation based on raw physical timing constraints under the right circumstances (overdriven, etc.)?
When one damps out a control loop to capture the voltage control characteristic (for example), while only having a single appreciable bump in the control sequence, one learns about resonance and oscillations in control loops.
You saying things, among men, like "silly hand waving" is pretty unprofessional.
Yup. I simulated and designed my first closed-loop control system when I was 19. It was 32,000 horsepower.
The opamp has a gain-bandwidth product of 800 KHz. The transistor is oscillating at 100 MHz. The loop gain/phase behavior is irrelevant.
Well, he hasn't explained what he meant. And he won't.
We must be talking about different things. I'm talking about a current source. We built it and it oscillated and we fixed it, and JT said really stupid stuff about it that he refuses to explain.
If you mean your fast 555, no, I didn't build that.
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