resetting a filter

Expand your mind, or start thinking about using a twisted pair of

The time delay that you get will vary a bit with delay from the reset, or - to put it another way - the reset action will mess with the action of the delay circuit for a few nanoseconds after it's removed. A double-terminated transmission line will probably have a shorter hangover.

-- Bill Sloman, Nijmegen

back to Q looks like a forward biased c-b current path?

Who'd bother posting an LTSpice model of high frequency circuit where the inductors didn't have any parallel capacitance - where you'd expect about 1pF - nor the resistors either - though that would be closer to 0.1pF?

-- Bill Sloman, Nijmegen

Hmm, how close could you space traces in a zig-zaggy pattern? You could add some taps, or short out some of the loops, for fine tuning. (But I guess that screws up the impedance, having some extra C flapping around on the end of a trace.) Could you squeeze a few feet of delay into a few square inches of PCB? With a multilayer board could you have zig-zags top and bottom. Does changing the transmission line impedance change the propigation velocity? (I'd not be surprised if skinny little low C traces were faster.... but I just don't know.)

George H.

-Lasse

No, but buried tracks (strip-line) are non-dispersive, and the the propagation delay is solely a function of the dielectric constant of the board material, rather than a messy hybrid as it is with track on the surface of the board (microstrip).

-- Bill Sloman, Nijmegen

to Q looks like a forward biased c-b current path?

I would. That's because I design electronics and you don't.

When I build this - and I will - the actual waveforms will be nearly identical to the sim, and it will work. This will be used in our fifth laser driver design, since we started doing laser drivers.

Apologies for using the word "work" in your presence.

Oh, you are way over-guessing the capacitance of a 330 nH surface-mount inductor. It will be more like 0.2 pF, small enough to ignore here.

Expand back into the days of hand-wired NIM boxes? Google "surface mount" to see what's happening this millenium. Google "skin loss" while you're at it.

My people can pick-and-place four parts in maybe 1% of the time it would take to fab/strip/solder/pack away a twisted pair. What a mess for production.

Apologies for using "production" in your presence.

Adding the diode greatly reduces the variation in delay as a function of rep-rate, which is what I'm going to do.

John Larkin schrieb:

Hello,

what about using a delay line as a small part?

Bye

Susumu has some interesting thin film passive parts for that delay range. Not particularly cheap.

PCB surface area and layers are expensive, and nanoseconds of delay use a lot of real estate. If you put the zigzags too close together, you get sideways coupling that makes things ugly.

Lumped RLC parts pack a lot of delay into a tiny area, and you can change them easily if required.

PCB traces make rotten delay lines. They are big, lossy, expensive, and have terrible TCs.

Microstrip (surface lines) do change velocity as a function of impedance. Lossless stripline (embedded) lines depend only on dielectric constant, but skin-effect losses make their prop delay complex in real life, too.

We sometimes zigzag a trace to equalize routing lengths in, say, a really high speed differential pair. But serious length PCB delay lines rarely make sense.

This board has a couple, near P1 and U5.

The CMOS silicon delay lines that I've used had a lot of jitter and bad TCs and were expensive. I can do an RLC in less area and for a tenth the price.

The Micrel parts are quite good, but are expensive ECL power hogs.

Haven't seen an answer to my question (above).

Also. What CMOS logic family? ...Jim Thompson

Oh, dear, the colours on that layout clash with, well, anything. ;)

Cheers

Phil Hobbs

I think it would make a great t-shirt.

Why don't we see t-shirts screened with PCB layouts? They are the true art of modern times.

.highlandtechnology.com=A0 jlarkin at highlandtechnology dot com

OK, thanks for the nice reply.

I'll chalk it up as another silly idea.

George H.

Incwww.highlandtechnology.com  jlarkin at highlandtechnology dot com

It's not silly; you just have to do the numbers for specific cases. Usually, lumped components win over distributed ones, but that's not always true. 100 ps delay might be reasonable for a pcb trace delay line.

I can almost see this little zig-zag pattern, with a bunch of ground traces between to prevent coupling, and a series of SMT FETs at one end to short out segment to allow programmable delay...

Charlie

Keep it simple. A gate will give a delay, a Schmitt trigger will give more (larger logic swing required). An R-C-Schmitt trigger combination will give larger delays yet, but none will delay a positive edge more than a negative edge (which seems to be desired here...). You might use a S/R flipflop to receive the Q-plus-delay and /Q outputs, if that's the intention.

Classically, a twisted-pair length of wire would be good, but that's not a component that can be pick-n-place assembled by a robot for you.

to Q looks like a forward biased c-b current path?

Version 4 SHEET 1 880 680 WIRE 112 -240 -16 -240 WIRE 240 -240 192 -240 WIRE 656 -240 320 -240 WIRE 752 -240 656 -240 WIRE 816 -240 752 -240 WIRE 656 -208 656 -240 WIRE 384 -144 256 -144 WIRE 416 -144 384 -144 WIRE 544 -144 496 -144 WIRE 544 -112 544 -144 WIRE 656 -112 656 -144 WIRE 256 -48 256 -144 WIRE 384 -48 384 -144 WIRE -16 -32 -16 -240 WIRE 16 -32 -16 -32 WIRE -16 96 -16 -32 WIRE 256 96 256 16 WIRE 256 96 -16 96 WIRE 384 96 384 16 WIRE 656 96 384 96 WIRE 656 144 656 96 WIRE 752 144 656 144 WIRE 800 144 752 144 WIRE -16 160 -16 96 WIRE 656 176 656 144 WIRE 256 208 256 96 WIRE 384 208 384 96 WIRE -16 272 -16 240 WIRE 656 272 656 240 WIRE 256 400 256 272 WIRE 384 400 384 272 WIRE 384 400 256 400 WIRE 448 400 384 400 WIRE 592 400 528 400 WIRE 592 432 592 400 FLAG -16 272 0 FLAG 656 272 0 FLAG 656 -112 0 FLAG 752 144 OUT FLAG 752 -240 REF FLAG 16 -32 IN FLAG 544 -112 0 FLAG 592 432 0 SYMBOL cap 640 176 R0 SYMATTR InstName C1 SYMATTR Value 10p SYMBOL voltage -16 144 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 -441 -22 Left 2 SYMATTR Value PULSE(0 3.3 1n 400p 400p 5n 10n 2) SYMATTR InstName V1 SYMBOL diode 240 -48 R0 SYMATTR InstName D2 SYMATTR Value DID SYMBOL ind 96 -224 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 330n SYMBOL res 336 -256 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL cap 640 -208 R0 SYMATTR InstName C2 SYMATTR Value 10p SYMBOL diode 368 -48 R0 SYMATTR InstName D1 SYMATTR Value DID SYMBOL diode 368 208 R0 SYMATTR InstName D3 SYMATTR Value DID SYMBOL diode 240 208 R0 SYMATTR InstName D4 SYMATTR Value DID SYMBOL current 496 -144 R90 WINDOW 0 -32 40 VBottom 2 WINDOW 3 32 40 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I1 SYMATTR Value 6m SYMBOL current 448 400 R270 WINDOW 0 32 40 VTop 2 WINDOW 3 -32 40 VBottom 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I2 SYMATTR Value 18m TEXT -288 -72 Left 2 !.tran 30n TEXT -616 0 Left 2 !.model DID D(Vfwd=0.3 Ron=12 Roff=1G Cjo=0.2p)