Spice Model Problems?

You mean the PLL/VCO? I thought someone had done a model for that, but I'm game. It's mostly digital but I'll at least take a peek. Those things are easy in PSpice, due to its digital primitives that are lacking in other Spice's. But I can make Analog logic ;-) ...Jim Thompson

How about the AD608 mixer IF chip? AFAIK none of those have decent Spice models. The SA614 sure doesn't. (That's one of my faves--I use it all over the place.)

Cheers

Phil Hobbs

TL431 (and TLV-) that exhibit actual compensation behavior.

Tim

-- Deep Friar: a very philosophical monk. Website:

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

EVERY MODEL !!!!

They never give you accurate match to the noise characteristics!

I'd like to be able to put the amp in the circuit, step it up or down to simulate the AC swing, and watch the noise.

Pick a good low noise, linear. LT1115 with its 1nV/rtHz, or the popular TI amp with 3nV/rtHz, I only need enough gain match to make certain the noise at the output is caused by the way I used the OpAmp.

The AD8014 model is really, really bad.

ZTX415. The published subcircuit works, but bears little resemblance, either to app notes, or real life.

I recall exchanging a subcircuit and some LTspice-derived plots with you. Did it run any more realistically in Pspice?

Some basic 741's really suck - they can deliver amps with no power supply draw (I didn't bother to check the rest)

Transistors with avalanche characteristics.

I got there ahead of you ;-)

-- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)

Not having a 4046 at hand, and the data sheet is sorely lacking, could someone measure the voltages at pins 11 and 12, versus VCC?

Thanks! ...Jim Thompson

Thanks! That will allow me to also observe its droop versus set current. ...Jim Thompson

A "preliminary" model:-

.subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin

• r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
• OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
• PARAMS: MNTYMXDLY=0 IO_LEVEL=0
• Rin=1Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10
• Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10

• Rin = VCO Input Resistace

• S1 = Voltage Limiter linear slope
• S2 = Voltage Limiter non-linear slope
• Vx = Input threshold voltage (between S1 and S2)
• Kb = Arbitrary constant to adjust the value of the conversion gain (transimpedance gain)
• Vfree= Frequency dependent constant in Emult
• Kc = Negative inverse amplitude of the square wave
• Vt = Trigger voltage of Schmitt trigger (not used)
• Vxqr = Amplitude of square wave (not used)
• M1 = Current mirror multiplier to adjust oscillator frequency
• M2 = Current mirror multiplier to adjust oscillator frequency

• Preliminary model still under development based on Natinal Semiconductor CD4046BM

• RAPerez 9/98

• Phase detector section

U1 INVA(4) DPWR DGND sigin compin isigin icompin

• isigin icompin clk1 clk2
• INVA_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL INVA_TIMING UGATE

U2 XOR DPWR DGND isigin icompin xorout

• XOR_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL XOR_TIMING UGATE

U3 NAND(2) DPWR DGND q1 q2 pclr

• NAND_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL NAND_TIMING UGATE (tplhty=1n tphlty=1n)

U4 DFF(1) DPWR DGND $D_HI clr clk1 $D_HI q1 qb1

• DFF1_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DFF1_TIMING UEFF tppcqlhty=4n tppcqhlty=4n tpclkqlhty=4n tpclkqhlty=4n

U5 DFF(1) DPWR DGND $D_HI clr clk2 $D_HI q2 qb2

• DFF2_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DFF2_TIMING UEFF tppcqlhty=5n tppcqhlty=5n tpclkqlhty=5n tpclkqhlty=5n

U7 BUFA(2) DPWR DGND fq1 fq2 s1 s2

• BUFA_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL BUFA_TIMING UGATE

ST2 vdd phcmpii s1 0 swt SB2 phcmpii vss s2 0 swt

.model swt VSWITCH (ROFF=2G RON=10m VOFF=0.8 VON=3.0)

U6 AND(2) DPWR DGND pclr reset clr

• AND_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL AND_TIMING UGATE

Ureset STIM(1,1) DPWR DGND

• reset
• IO_HCT
• +0s 0
• 2ns 1
• 1s 1

U8 NOR(2) DPWR DGND fq1 fq2 norout

• NOR_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL NOR_TIMING UGATE

U9 ANDA(2,2) DPWR DGND q1 od1 q2 od2 fq1 fq2

• ANDA_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL ANDA_TIMING UGATE

U10 DLYLINE DPWR DGND q1 od1

• DLY_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 DLYLINE DPWR DGND q2 od2
• DLY_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL DLY_TIMING UDLY dlyty=12n

U12 BUFA(3) DPWR DGND norout xorout vcosqr phpls phcmpi vcoout

• BUFB_TIMING IO_HCT
• MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.MODEL BUFB_TIMING UGATE

• VCO Section

Rin vcoin vss {Rin} Evlim vlim 0 value={if(v(vcoin,vss)

Will run under PSpice, but nothing else. (MNTYMXDLY)

...Jim Thompson

Scary Spice?

-- Paul Hovnanian mailto: snipped-for-privacy@Hovnanian.com

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Got delayed by paying work ;-)

Could someone 'scope each end of the VCO timing cap (C1, pins 6 & 7) and tell me what they look like? (The block diagram implies a physical impossibility, so there's something limiting the pull-down switches to some voltage. A waveform will expose the "secret" :)

Thanks! ...Jim Thompson