a little filter

We make a box that can output a lot of fiberoptic logic signals, light on/off. One existing mode is PWM, where frequency is 125 MHz/N, and "on" resolution is 1 ns. I have a customer who needs a remote analog signal, 0-1 volt, that he can update in a microsecond or two. He'd like 10 bit resolution.

So I figured that an optical/electrical converter could drive a lowpass filter at the far end, so I built him the filter to try. We did a test board a while back, and we tossed some extra circuits onto the layout, including a little filter board.

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Seems to work. I'm running at N=32, PWM frequency 3.9 MHz, which gives us 256 step (8 bit) resolution. I can't get a lowpass filter design to work at 512 steps/9 bits/2 MHz.

PWM-to-DC has awful dilemmas. To get N steps of resolution, you need a lowpass filter that will settle to 1/N volts in the time budget, and have p-p ripple about that same magnitude. That turns out to be awful, an n-squared dilemma at best. It needs to be a Bessel filter, or it will ring and wreck the settling time. Bessels let a lot of PWM ripple leak through. Higher order filters reduce ripple some but add time delay.

A better answer is PWM with some sort of ramp and s/h instead of the lowpass, but that's a non-trivial design and a PCB layout. Even better would be to hack the source FPGA to transmit a burst of digital data, and have a decoder+DAC at the far end... again, a bunch of design.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin
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You need Williams and Taylor's "Electronic Filter Design Handbook"

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It is isn't cheap, but everybody here who knows what they are talking about swears by it.

High order Bessell filters do have up to about four times the time delay of a first order filter, but the ripple attenuation goes up much more rapidly with the order of the filter. There are also equi-ripple variants of the pure Bessel filter.

One can also choose the pulse width modulation pattern to minimise the lower frequency ripple components. Sigma Delta modulators have always exploited this since they were invented.

My 1996 paper spelled out a less thorough-going approach optimised for a different situation - fewer (power-dissipating) switching transitions - and not as much minimisation of the lower frequency ripple content.

Sloman A.W., Buggs P., Molloy J., and Stewart D. "long title" Measurement Science and Technology, 7 1653-64

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Bill Sloman, Sydney
Reply to
Bill Sloman

I am not sure if you are asking something.

You're right that filter order increases the delay, ceteris paribus, and it Bessel or Bessel-like helps to minimize ringing. But you seem to want a low-pass filter, which a Bessel is quite nominally (and by accident: its pu rpose is constant delay, not low-pass).

I played with something that has 1.0 ms equi-ripple delay, that could be sc aled. Other things are possible. If you want more rejection, some TX zeros obviously "do something."

Linear phase low-pass filter Equal ripple delay passband Low frequency delay = 1.000000 msec Upper passband edge frequency = 0.001000 MHz Delay ripple =18.022361 usec Passband edge frequency = 0.001000 MHz equal minima stop band with edge frequency= 0.001500 MHz multiplicity of zero at infinity = 2 number of finite transmission zero pairs = 2 overall filter degree = 6 transmission zeros real part imaginary part 0.0000000D+00 2.0999615D+03 0.0000000D+00 1.5476704D+03

1 +---R---+ 50.000000 ohm 2 | L 8.615928 mH 3 +---C---+ 3.325297 uF | .-+. 4 | L C 15.173470 mH res.frequency | `-+' 378.558212 nF 0.002100 MHz 5 +---C---+ 18.380877 uF | .-+. 6 | L C 12.409140 mH res.frequency | `-+' 852.200167 nF 0.001548 MHz 7 +---C---+ 3.091728 uF 9 +---R---+ 50.017324 ohm
Reply to
Simon S Aysdie

It's a discussion group.

Williams calls lowpass Bessels lowpass filters, and I do too. He says (sec 7.3 of 4e) that lowpass filters, including Bessels, are not the most efficient delay lines.

I Spiced that. It's down 3 dB at 393 Hz, so I can scale its frequency response about 1000:1 and compare it to my 350K 3-pole Bessel.

Your scaled 0.1% settling time is about 3.8 us, compared to about 2.7 for the Bessel. Those added stages add delay. The big difference is of course frequency rolloff; my 3p Bessel is -60 dB at 4.8 MHz, and yours is -60 at the equivalent of 1.4 MHz.

It looks like sort of a wash. Your filter could allow me to PWM at a lower frequency before the ripple gets big, improving resolution, but the added settling time compromises the improvement. The advantage of the 3p Bessel is that it's easy to make from a few available parts; higher-order filters require multiple inductor values with, often, inconvenient ratios.

Like I said, PWM is awful. The more complex filter squeezes out maybe one more bit of analog signal resolution.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation
Reply to
John Larkin

Do you have to use simple PWM?

If you encode the transmitted signal with a sigma-delta modulator the ripple frequency will be much higher for most codes. There will unfortunately be some values that will still give the same ripple as PWM.

kevin

Reply to
kevin93

I don't really understand delta-sigma dacs. The density of rising and falling edges will vary continuously, and it would take extreme rise/fall speed and symmetry to deliver an accurate average value. I suspect that real d-s dacs use some sort of charge dispensing tricks, rather than just lowpass filtering a rail-to-rail logic swing.

But I certainly can't process 1 ns pulses. I wonder what d-s clock rate it would take to get, say, a 10-bit equivalent ADC that settles in a couple of microseconds. It would still have the existing filtering problem, namely good rolloff (to kill the d-s noise, similar to killing the PWM carrier) but fast step response settling. Audio dacs don't have that same problem, so can use agressive filters.

The PWM facility already exists in our FPGA. If we go in and redesign things, we may as well just pump out a serial digital data stream, and use a DAC on the other end. The issue then becomes how best to encode it.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation
Reply to
John Larkin

On a sunny day (Thu, 20 Feb 2014 20:51:26 -0800) it happened John Larkin wrote in :

How about a shift register with a R2R network at the other end? So end the 'byte' serially.

I have done R2R on CMOS output, it works, that vertical white thing is one:

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Circuit diagram, IC9 (right) is the R2R ladder:

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There is a simple filter in there too.. Should work for highter frequencies than 3.5 kHz too..

Reply to
Jan Panteltje

it

of

but

se

e:

None of that makes much sense to me, in this context.

It did set me thinking though. John Larkin's filter problem is that he want s a complex and hard to realise fast-settling filter, at a frequency where reactive components are far from ideal.

If he used a clocked shift register as a digital delay line with a resistor on every tap, and ran the other ends of the resistors into a summing junct ion, he's built an FIR filter, and 0.1% resistors on the E96 grid can give you a high-order filter characteristic with relatively little effort (and b oard space).

Finite-impulse response filters have very good transient behaviour.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

or on every tap, and ran the other ends of the resistors into a summing jun ction, he's built an FIR filter, and 0.1% resistors on the E96 grid can giv e you a high-order filter characteristic with relatively little effort (and board space).

As a frank newbie at this, the resistors seem to make sense...Are there eno ugh digital output lines on the FPGA to do it directly, by switching a resi stor network?

Reply to
haiticare2011

On a sunny day (Fri, 21 Feb 2014 03:38:43 -0800 (PST)) it happened Bill Sloman wrote in :

Well I should have read it better, I think just go serial some format and DAC (that could be R2R). FPGAs have these very high clock speed outputs, soo, and that is some sort of standard, but I never worked with that, Resistors work into the GHz very nicely. PWM sucks for high speeds and high accuracy. But he was talking about 'a few us', so any fast UART sort of thing, clock recovery with some flops or flips, done that, and then only filter below Niquist /2, shift register with buffer works too, 10 bits maybe, but why not. Trimpots :-) No difficult filters...

Yea, I think I would like to hear what it is used for, or at least what sort of speeds and accuracy are needed.

Reply to
Jan Panteltje

On a sunny day (Fri, 21 Feb 2014 05:22:06 -0800 (PST)) it happened snipped-for-privacy@gmail.com wrote in :

Yes, that is an R2R right there, for video, left to the TO220 LM317:

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8 bits, but OK, why not ten. Dunno how many pins he has.
Reply to
Jan Panteltje

Putting a delta-sigma dither on a shorter-period PWM doesn't have either of those problems. (A trick I learned from Tim Wescott a few years ago and have used often since then.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

There must be some sort of hybrid codings, like d-s but with a limited number of edges.

Suppose I have 1 ns resolution (1 GHz clock) and make 1 MHz PWM. That gives me

0.1% resolution. If I want to make 0.501 volts, simple PWM is 501 highs and 499 lows. But that has a whopping 1 MHz ripple.

I can get the same output from 250 high, 250 low, 251 high, and 249 low. Only 4 edges and the ripple is now mostly 2 MHz, easier to filter. That's not precisely a dither, just a different way to code 501 highs.

Oh, we're about to test our gadget that dithers a 16-bit DAC down to microvolt resolution, discussed here previously. The DAC clock rate is 48 MHz and the dither waveform is a sine wave at 13.0078 MHz, which is 1110 cycles of sine wave painted into a 4K RAM, about 8 LSBs p-p. I figure on using a spectrum analyzer to see if it works.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation
Reply to
John Larkin

Den torsdag den 20. februar 2014 23.35.22 UTC+1 skrev John Larkin:

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heres a hacked together example of pwm, pwm with reference count reversed a nd a simple delta sigma

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2624 -112 1920 -112 WIRE -208 -96 -208 -464 WIRE 64 -96 64 -272 WIRE 64 -96 -208 -96 WIRE 96 -96 64 -96 WIRE 2864 -96 2880 -128 WIRE 2624 -80 2624 -112 WIRE 2672 -80 2624 -80 WIRE 224 -64 224 -112 WIRE 272 -64 224 -64 WIRE 2800 -64 2800 -144 WIRE 2800 -64 2736 -64 WIRE 864 -48 336 -48 WIRE 1360 -48 1024 -48 WIRE 1920 -48 1920 -112 WIRE 1920 -48 1360 -48 WIRE 2304 -48 2304 -1664 WIRE 2640 -48 2640 -224 WIRE 2640 -48 2304 -48 WIRE 2672 -48 2640 -48 WIRE 240 -32 240 -176 WIRE 240 -32 -64 -32 WIRE 272 -32 240 -32 WIRE 2800 -16 2800 -64 WIRE 2848 -16 2800 -16 WIRE 816 0 816 -368 WIRE 864 0 816 0 WIRE 2816 16 2816 -128 WIRE 2816 16 2512 16 WIRE 2848 16 2816 16 WIRE -64 32 -64 -32 WIRE 576 32 -64 32 WIRE 80 48 32 48 WIRE 80 64 48 64 WIRE 576 80 576 32 WIRE 576 80 432 80 WIRE 2512 80 2512 16 WIRE 3152 80 2512 80 WIRE 368 96 352 96 WIRE 2656 96 2608 96 WIRE 2656 112 2624 112 WIRE 2944 112 2720 112 WIRE 3152 128 3152 80 WIRE 3152 128 3008 128 WIRE 2944 144 2928 144 WIRE 208 160 256 144 WIRE 352 160 352 96 WIRE 352 160 320 144 WIRE 224 176 256 160 WIRE 272 208 272 192 WIRE 2784 208 2832 192 WIRE 2928 208 2928 144 WIRE 2928 208 2896 192 WIRE -432 224 -432 -1520 WIRE 32 224 32 48 WIRE 32 224 -432 224 WIRE 80 224 32 224 WIRE 2800 224 2832 208 WIRE 208 240 208 160 WIRE 208 240 144 240 WIRE -288 256 -336 256 WIRE -208 256 -208 -96 WIRE -208 256 -224 256 WIRE 48 256 48 64 WIRE 48 256 -208 256 WIRE 80 256 48 256 WIRE 1984 256 1984 -1520 WIRE 2608 256 2608 96 WIRE 2608 256 1984 256 WIRE 2848 256 2848 240 WIRE 2608 272 2608 256 WIRE 2656 272 2608 272 WIRE -288 288 -288 272 WIRE 208 288 208 240 WIRE 256 288 208 288 WIRE 2784 288 2784 208 WIRE 2784 288 2720 288 WIRE 864 304 320 304 WIRE 1360 304 1024 304 WIRE 1984 304 1984 256 WIRE 1984 304 1360 304 WIRE 2368 304 2368 -1312 WIRE 2624 304 2624 112 WIRE 2624 304 2368 304 WIRE 2656 304 2624 304 WIRE -16 320 -80 320 WIRE 224 320 224 176 WIRE 224 320 48 320 WIRE 256 320 224 320 WIRE 2784 336 2784 288 WIRE 2832 336 2784 336 WIRE 816 352 816 0 WIRE 864 352 816 352 WIRE 2528 368 2496 368 WIRE 2800 368 2800 224 WIRE 2800 368 2608 368 WIRE 2832 368 2800 368 WIRE 816 496 816 352 WIRE 1200 496 1200 -1904 WIRE 1200 496 816 496 WIRE 816 640 816 496 WIRE 2176 672 2176 -768 WIRE 2928 672 2176 672 WIRE 3232 672 3008 672 WIRE 3008 688 3008 672 WIRE 2240 800 2240 -416 WIRE 2928 800 2240 800 WIRE 3008 800 3008 768 WIRE 3008 832 3008 800 WIRE 2304 928 2304 -48 WIRE 2928 928 2304 928 WIRE 3008 928 3008 912 WIRE 3008 960 3008 928 WIRE 2368 1072 2368 304 WIRE 2928 1072 2368 1072 WIRE 3008 1072 3008 1040 WIRE 3008 1184 3008 1152 WIRE 2240 1232 2240 800 WIRE 2368 1232 2368 1072 WIRE 2304 1328 2304 928 WIRE 2176 1344 2176 672 WIRE 2176 1520 2176 1424 WIRE 2240 1520 2240 1312 WIRE 2304 1520 2304 1408 WIRE 2368 1520 2368 1312 FLAG 96 112 0 FLAG 112 288 0 FLAG 272 208 0 FLAG 288 352 0 FLAG 384 128 0 FLAG 112 -240 0 FLAG 128 -64 0 FLAG 288 -144 0 FLAG 304 0 0 FLAG 400 -224 0 FLAG 112 -608 0 FLAG 128 -432 0 FLAG 288 -512 0 FLAG 304 -368 0 FLAG 400 -592 0 FLAG 128 -960 0 FLAG 144 -784 0 FLAG 304 -864 0 FLAG 320 -720 0 FLAG 416 -944 0 FLAG 960 -672 0 FLAG 960 -320 0 FLAG 944 48 0 FLAG 944 400 0 FLAG 944 256 0 FLAG 944 -96 0 FLAG 960 -464 0 FLAG 960 -816 0 FLAG -80 320 0 FLAG -16 336 0 FLAG 816 720 0 FLAG 2672 160 0 FLAG 2688 336 0 FLAG 2848 256 0 FLAG 2864 400 0 FLAG 2960 176 0 FLAG 2688 -192 0 FLAG 2704 -16 0 FLAG 2864 -96 0 FLAG 2880 48 0 FLAG 2976 -176 0 FLAG 2688 -560 0 FLAG 2704 -384 0 FLAG 2864 -464 0 FLAG 2880 -320 0 FLAG 2976 -544 0 FLAG 2704 -912 0 FLAG 2720 -736 0 FLAG 2880 -816 0 FLAG 2896 -672 0 FLAG 2992 -896 0 FLAG 2496 368 0 FLAG 2672 -1456 0 FLAG 2688 -1280 0 FLAG 2848 -1360 0 FLAG 2864 -1216 0 FLAG 2960 -1440 0 FLAG 2688 -1808 0 FLAG 2704 -1632 0 FLAG 2864 -1712 0 FLAG 2880 -1568 0 FLAG 2976 -1792 0 FLAG 2688 -2176 0 FLAG 2704 -2000 0 FLAG 2864 -2080 0 FLAG 2880 -1936 0 FLAG 2976 -2160 0 FLAG 2704 -2528 0 FLAG 2720 -2352 0 FLAG 2880 -2432 0 FLAG 2896 -2288 0 FLAG 2992 -2512 0 FLAG 2496 -1248 0 FLAG -336 256 0 FLAG -288 288 0 FLAG 2176 1520 0 FLAG 2240 1520 0 FLAG 2304 1520 0 FLAG 2368 1520 0 FLAG 1360 304 b0 FLAG 1360 -48 b1 FLAG 1360 -416 b2 FLAG 1360 -768 b3 FLAG 1920 -3392 0 FLAG 1936 -3216 0 FLAG 2096 -3296 0 FLAG 2112 -3152 0 FLAG 2208 -3376 0 FLAG 1936 -3744 0 FLAG 1952 -3568 0 FLAG 2112 -3648 0 FLAG 2128 -3504 0 FLAG 2224 -3728 0 FLAG 1936 -4112 0 FLAG 1952 -3936 0 FLAG 2112 -4016 0 FLAG 2128 -3872 0 FLAG 2224 -4096 0 FLAG 1952 -4464 0 FLAG 1968 -4288 0 FLAG 2128 -4368 0 FLAG 2144 -4224 0 FLAG 2240 -4448 0 FLAG 2784 -4176 0 FLAG 2784 -3824 0 FLAG 2768 -3456 0 FLAG 2768 -3104 0 FLAG 2768 -3248 0 FLAG 2768 -3600 0 FLAG 2784 -3968 0 FLAG 2784 -4320 0 FLAG 2784 -4448 0 FLAG 2784 -4592 0 FLAG 3968 -4544 vo3 FLAG 5584 -2912 0 FLAG 5584 -3360 vo3 FLAG 5584 -2640 vo2 FLAG 5584 -2080 vo1 FLAG 3008 1184 0 FLAG 3808 -4448 0 FLAG 3808 -4592 0 FLAG 3824 -2464 0 FLAG 3824 -2608 0 FLAG 3824 -848 0 FLAG 3824 -992 0 FLAG 4016 -944 vo1 FLAG 4016 -2560 vo2 FLAG 3728 -4448 0 FLAG 3744 -2464 0 FLAG 3744 -848 0 FLAG 5920 -2912 0 FLAG 6272 -2896 0 FLAG 5584 -2192 0 FLAG 5920 -2192 0 FLAG 6272 -2176 0 FLAG 5584 -1632 0 FLAG 5920 -1632 0 FLAG 6272 -1616 0 FLAG 6208 -3024 dsm FLAG 6208 -2304 pwmrev FLAG 6192 -1744 pwm SYMBOL Digital\\and 112 16 R0 SYMATTR InstName A1 SYMBOL Digital\\xor 128 192 R0 SYMATTR InstName A2 SYMBOL Digital\\xor 304 256 R0 SYMATTR InstName A3 SYMBOL Digital\\or 400 32 R0 SYMATTR InstName A4 SYMBOL Digital\\and 288 96 R0 SYMATTR InstName A5 SYMBOL Digital\\and 128 -336 R0 SYMATTR InstName A6 SYMBOL Digital\\xor 144 -160 R0 SYMATTR InstName A7 SYMBOL Digital\\xor 320 -96 R0 SYMATTR InstName A8 SYMBOL Digital\\or 416 -320 R0 SYMATTR InstName A9 SYMBOL Digital\\and 320 -272 R0 SYMATTR InstName A10 SYMBOL Digital\\and 128 -704 R0 SYMATTR InstName A11 SYMBOL Digital\\xor 144 -528 R0 SYMATTR InstName A12 SYMBOL Digital\\xor 320 -464 R0 SYMATTR InstName A13 SYMBOL Digital\\or 416 -688 R0 SYMATTR InstName A14 SYMBOL Digital\\and 304 -624 R0 SYMATTR InstName A15 SYMBOL Digital\\and 144 -1056 R0 SYMATTR InstName A16 SYMBOL Digital\\xor 160 -880 R0 SYMATTR InstName A17 SYMBOL Digital\\xor 336 -816 R0 SYMATTR InstName A18 SYMBOL Digital\\or 432 -1040 R0 SYMATTR InstName A19 SYMBOL Digital\\and 320 -960 R0 SYMATTR InstName A20 SYMBOL Digital\\dflop 944 256 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A21 SYMBOL Digital\\dflop 944 -96 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A22 SYMBOL Digital\\dflop 960 -464 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A23 SYMBOL Digital\\dflop 960 -816 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A24 SYMBOL Digital\\inv -16 256 R0 SYMATTR InstName A25 SYMBOL voltage 816 624 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 1u .1n .1n 50n 100n) SYMBOL Digital\\and 2688 64 R0 SYMATTR InstName A26 SYMBOL Digital\\xor 2704 240 R0 SYMATTR InstName A27 SYMBOL Digital\\xor 2880 304 R0 SYMATTR InstName A28 SYMBOL Digital\\or 2976 80 R0 SYMATTR InstName A29 SYMBOL Digital\\and 2864 144 R0 SYMATTR InstName A30 SYMBOL Digital\\and 2704 -288 R0 SYMATTR InstName A31 SYMBOL Digital\\xor 2720 -112 R0 SYMATTR InstName A32 SYMBOL Digital\\xor 2896 -48 R0 SYMATTR InstName A33 SYMBOL Digital\\or 2992 -272 R0 SYMATTR InstName A34 SYMBOL Digital\\and 2896 -224 R0 SYMATTR InstName A35 SYMBOL Digital\\and 2704 -656 R0 SYMATTR InstName A36 SYMBOL Digital\\xor 2720 -480 R0 SYMATTR InstName A37 SYMBOL Digital\\xor 2896 -416 R0 SYMATTR InstName A38 SYMBOL Digital\\or 2992 -640 R0 SYMATTR InstName A39 SYMBOL Digital\\and 2880 -576 R0 SYMATTR InstName A40 SYMBOL Digital\\and 2720 -1008 R0 SYMATTR InstName A41 SYMBOL Digital\\xor 2736 -832 R0 SYMATTR InstName A42 SYMBOL Digital\\xor 2912 -768 R0 SYMATTR InstName A43 SYMBOL Digital\\or 3008 -992 R0 SYMATTR InstName A44 SYMBOL Digital\\and 2896 -912 R0 SYMATTR InstName A45 SYMBOL Digital\\and 2688 -1552 R0 SYMATTR InstName A47 SYMBOL Digital\\xor 2704 -1376 R0 SYMATTR InstName A49 SYMBOL Digital\\xor 2880 -1312 R0 SYMATTR InstName A50 SYMBOL Digital\\or 2976 -1536 R0 SYMATTR InstName A51 SYMBOL Digital\\and 2864 -1472 R0 SYMATTR InstName A52 SYMBOL Digital\\and 2704 -1904 R0 SYMATTR InstName A53 SYMBOL Digital\\xor 2720 -1728 R0 SYMATTR InstName A54 SYMBOL Digital\\xor 2896 -1664 R0 SYMATTR InstName A55 SYMBOL Digital\\or 2992 -1888 R0 SYMATTR InstName A56 SYMBOL Digital\\and 2896 -1840 R0 SYMATTR InstName A57 SYMBOL Digital\\and 2704 -2272 R0 SYMATTR InstName A58 SYMBOL Digital\\xor 2720 -2096 R0 SYMATTR InstName A59 SYMBOL Digital\\xor 2896 -2032 R0 SYMATTR InstName A60 SYMBOL Digital\\or 2992 -2256 R0 SYMATTR InstName A61 SYMBOL Digital\\and 2880 -2192 R0 SYMATTR InstName A62 SYMBOL Digital\\and 2720 -2624 R0 SYMATTR InstName A63 SYMBOL Digital\\xor 2736 -2448 R0 SYMATTR InstName A64 SYMBOL Digital\\xor 2912 -2384 R0 SYMATTR InstName A65 SYMBOL Digital\\or 3008 -2608 R0 SYMATTR InstName A66 SYMBOL Digital\\and 2896 -2528 R0 SYMATTR InstName A67 SYMBOL Digital\\buf1 -288 192 R0 SYMATTR InstName A46 SYMBOL voltage 2176 1328 R0 WINDOW 3 -397 59 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 1 70u 1n 1n 80u 160u) SYMATTR InstName V2 SYMBOL voltage 2240 1216 R0 WINDOW 3 -445 43 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 1 30u 1n 1n 40u 80u) SYMATTR InstName V3 SYMBOL voltage 2304 1312 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V4 SYMATTR Value PULSE(0 1 10u 1n 1n 20u 40u) SYMBOL voltage 2368 1216 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V5 SYMATTR Value PULSE(0 1 0 1n 1n 10u 20u) SYMBOL voltage 2624 368 R90 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V6 SYMATTR Value 0.1 SYMBOL voltage 2624 -1248 R90 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V7 SYMATTR Value 0.1 SYMBOL Digital\\and 1936 -3488 R0 SYMATTR InstName A48 SYMBOL Digital\\xor 1952 -3312 R0 SYMATTR InstName A68 SYMBOL Digital\\xor 2128 -3248 R0 SYMATTR InstName A69 SYMBOL Digital\\or 2224 -3472 R0 SYMATTR InstName A70 SYMBOL Digital\\and 2112 -3408 R0 SYMATTR InstName A71 SYMBOL Digital\\and 1952 -3840 R0 SYMATTR InstName A72 SYMBOL Digital\\xor 1968 -3664 R0 SYMATTR InstName A73 SYMBOL Digital\\xor 2144 -3600 R0 SYMATTR InstName A74 SYMBOL Digital\\or 2240 -3824 R0 SYMATTR InstName A75 SYMBOL Digital\\and 2144 -3776 R0 SYMATTR InstName A76 SYMBOL Digital\\and 1952 -4208 R0 SYMATTR InstName A77 SYMBOL Digital\\xor 1968 -4032 R0 SYMATTR InstName A78 SYMBOL Digital\\xor 2144 -3968 R0 SYMATTR InstName A79 SYMBOL Digital\\or 2240 -4192 R0 SYMATTR InstName A80 SYMBOL Digital\\and 2128 -4128 R0 SYMATTR InstName A81 SYMBOL Digital\\and 1968 -4560 R0 SYMATTR InstName A82 SYMBOL Digital\\xor 1984 -4384 R0 SYMATTR InstName A83 SYMBOL Digital\\xor 2160 -4320 R0 SYMATTR InstName A84 SYMBOL Digital\\or 2256 -4544 R0 SYMATTR InstName A85 SYMBOL Digital\\and 2144 -4464 R0 SYMATTR InstName A86 SYMBOL Digital\\dflop 2768 -3248 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A87 SYMBOL Digital\\dflop 2768 -3600 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A88 SYMBOL Digital\\dflop 2784 -3968 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A89 SYMBOL Digital\\dflop 2784 -4320 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A90 SYMBOL Digital\\dflop 2784 -4592 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A91 SYMBOL res 5568 -3216 R0 SYMATTR InstName R17 SYMATTR Value 125 SYMBOL cap 5568 -2992 R0 SYMATTR InstName C1 SYMATTR Value 1.2n SYMBOL res 3024 1056 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R20 SYMATTR Value 1k SYMBOL res 3024 912 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R21 SYMATTR Value 1k SYMBOL res 3024 784 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R22 SYMATTR Value 1k SYMBOL res 3024 656 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R23 SYMATTR Value 1k SYMBOL res 2992 944 R0 SYMATTR InstName R24 SYMATTR Value 500 SYMBOL res 2992 816 R0 SYMATTR InstName R25 SYMATTR Value 500 SYMBOL res 2992 672 R0 SYMATTR InstName R26 SYMATTR Value 500 SYMBOL res 2992 1056 R0 SYMATTR InstName R27 SYMATTR Value 1k SYMBOL Digital\\dflop 3808 -4592 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A92 SYMBOL Digital\\dflop 3824 -2608 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A93 SYMBOL Digital\\dflop 3824 -992 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A94 SYMBOL cap 5904 -3008 R0 SYMATTR InstName C4 SYMATTR Value 8n SYMBOL res 6256 -3040 R0 SYMATTR InstName R9 SYMATTR Value 50 SYMBOL ind 5792 -3040 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L1

SYMBOL res 6144 -3040 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value 75 SYMBOL res 5568 -2496 R0 SYMATTR InstName R11 SYMATTR Value 125 SYMBOL cap 5568 -2272 R0 SYMATTR InstName C2 SYMATTR Value 1.2n SYMBOL cap 5904 -2288 R0 SYMATTR InstName C3 SYMATTR Value 8n SYMBOL res 6256 -2320 R0 SYMATTR InstName R12 SYMATTR Value 50 SYMBOL ind 5792 -2320 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L2

SYMBOL res 6144 -2320 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R13 SYMATTR Value 75 SYMBOL res 5568 -1936 R0 SYMATTR InstName R14 SYMATTR Value 125 SYMBOL cap 5568 -1712 R0 SYMATTR InstName C5 SYMATTR Value 1.2n SYMBOL cap 5904 -1728 R0 SYMATTR InstName C6 SYMATTR Value 8n SYMBOL res 6256 -1760 R0 SYMATTR InstName R15 SYMATTR Value 50 SYMBOL ind 5792 -1760 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L3

SYMBOL res 6144 -1760 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R16 SYMATTR Value 75 TEXT -112 584 Left 2 !.tran 1024u

Reply to
Lasse Langwadt Christensen

Well, the D-S extended PWM has exactly 2 transitions per cycle, and the cycles are, say, 32 times faster than the original PWM. You do lose a bit of linearity at the edges, where some of the time your data word is

0 or 0xFF, so there are no transitions.

That's pretty much what I mean, if you use a D-S register to count how many 250s and how many 251s.

I'd be interested to see how well it works.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

ht

ripple frequency will be much higher for most codes. There will unfortuna tely be some values that will still give the same ripple as PWM.

all

t

ust

e it

le of

ly

r)

em,

it.

mber of edges.

There is - I spelled it out in my 1996 paper (of which you have a copy).

If you make your simple PWM waveform by using a digital comparator to compa re your desired digital value with a continuously incrementing counter, you get one "high" and one "low" period in each cycle.

If you reverse the order of the higher order bits coming out of the counter before they get to the comparator, you get what you've asked for.

My application reversed the top four, so MSB went to MSB-3, MSB-1 went to M SB-2, MSB-2 went to MSB-1 and MSB-3 went to MSB.

The extreme PWM waveforms are still single negative or positive going spike s, but over most of the range you get 16 high and low periods, and a single bit increment makes just of of them narrower or wider.

es

s

Only

As discussed in my 1996 paper. Which has now been cited fifteen times (plus twice by me). At least one of the citing authors hadn't read it - or at le ast not very carefully - whence one of my self-citations. It's probably a l ittle long for John's attention span too.

10

--
Bill Sloman, Sydney
Reply to
Bill Sloman

Interesting idea, but it seems like it has a bad case of low-frequency birdies over most of its code space, compared with a four-bit delta-sigma extender.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Yeah, this is the familiar frequencyvoltage conversion that is used in auto tachometers. The problem is, you can send a ten-bit digital signal in ten blink times. You can send a ten-bit analog frequency update in 1000 blink times.

For a good conversion, it probably would suffice to start a ramp at pulse #1, and stop it (track/hold fashion) at pulse #1000. In short, do a single-slope conversion, backward. This will be easier than the filter problem, and has a similar limit on how fast the output updates.

Part-per-thousand accuracy will probably be easiest if you trim rather than find 0.1% capacitors. NP0 is nice and stable, and voltage references and precision resistors will hold a calibration pretty well. The trim can be on a resistor divider outside the integrator section.

Reply to
whit3rd

It's more than an idea - it worked in production for a number of years, unt il Thermoelectron decided that Affinity Sensors wasn't making them enough m oney, and closed it down.

As I pointed out when I wrote the paper, and John Larkin has observed in th is thread, the non-linearity of PWM DAC does depend on the number of transi tions per cycle, so you are trading off low frequency ripple against non-li nearity.

In my application, each transition also dumped the heat from the switching transient in my MOSFETs, which were switching a current that could go up to three amps. I limited the number of transitions to the point where the swi tching dissipation was as high as the static dissipation in the devices.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

'Twaren't my question, though. Vanilla PWM has been working fine in lots of applications, since well before 1996, but it has the nasty quadratic frequency vs. resolution tradeoff. Of course it keeps the same number of transitions per cycle as well, namely 2.

Your method has more transitions, but since they are spaced irregularly (very irregularly indeed for some codes), ISTM that it's only a partial solution to the problem.

The delta-sigma extended PWM wasn't my idea--I got it from Tim Wescott, as I said, and it probably wasn't original with him either. (If it was, Tim, I apologize in advance.) However, it works great, and keeps the low frequency schmutz to a minimum. A second-order D-S extender would do even better, but I haven't needed one so far.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

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