level shifter

John Larkin a écrit :

How low frequency do you need to go? Do you need DC?

Since the 10EP51 is a single FF, an alternative would be to servo its power supply down to drive the phemt directly and then level-shift the logic inputs into the FF. This is has the advantage of less demanding level shifting requirements.

Yes.

How about a low-tech cheapo solution? Like a TLV431:

Drive o-----o--------o-------oo | | | \ | | / | | \ | | / o o | TLV431| | o z --- o-------oA --- | | | o o o | | | \ o--------o-----------o PHEMT / | \ | / | | | o--------o

| \ / \ / | o o

-5V (created by AACircuit v1.28.6 beta 04/19/05

Provided that the Eclipse flop has a well defined DC output level that should make for a rather accurate absolute PHEMT drive level.

Something like this...

Eats all the unknown input levels.

Sprinkle bypasses appropriately to keep the current mirror from going bananas during the "jerk". ...Jim Thompson

I think we are currently playing with similar toys. I needed a reasonable pretrigger for the 54750A, max +-2V around gnd. Did a brute-force aproach with 4 BAT15 Schottky diodes into 50 Ohm.

Risetime was the same as the gate with normal termination, some 200 ps. Amplitude was cut in half from 800 to 400 mV, so the BAT15 must have

ATF-501 PHEMts & friends / Avago switch between 0 and +0.7V, that's less distance than for your phemt and would be even easier with 2.5V logic. Avago is available @ Digi-Key.

regards, Gerhard

Servo the shifted output common mode:

.--------. | | | Q |----------------------+---. | | | | | | | | | Q/|--+---. | | | | | | | | '--------' | .-. .-. | --- | | | | --- --- | | | | --- | '-' '-' | | | ___ ___ | | '---+-|___|-+-|___|-+---+---> PHEMT | | | |/ | |/ -2V >---|---------------| 2xBFT25... |> | |>

| | | .-. .--+ .-. | | | | | | | | --- | | | '-' --- | '-' /| || | | | | ___ /+|---< -0.3V .--||-+----+--|-------+---|___|--< | | || | \-|-. === | \| | GND '-----------------------'

I've used something like this before to change positive logic voltages to n= egative logic voltages. Gives reasonable speed with crap transistors. Not= too precise. I don't know if it can be adapted to your use. Proper output= voltages require setting the resistors properly.

IN =3D OUT =3D

That is cool. Nice.

I considered the e-phemts here, but (as I read the s-params, all they give us) they have a lot more input and output capacitance than the NEC parts. They still need level shifting to pretty good accuracy, so I'd still prefer the gate levels to be independent of the exact value of the 3.3 volt supply. We are playing with some of the higher power Avago parts (like, 1 amp) for another application.

I am stuck with 3.3 volt pecl here. It's a minor miracle that I can get this mess of 3.3 pecl, 2.5 pecl, 2.5 cml, cmos, and analog to talk friendly to one another. I sort of miss all-5-volt logic.

I have a bunch of part paper dolls taped to a sheet of vellum, scribbling pencil lines, trying to get all the logic to route without long traces or crossovers or confusing what's Q and what's Qbar. Blast from the past.

That's easy. Present chip design has _17_ power domains... NOTE, NOTE, NOTE: NOT my doing... that's what I inherited ;-)

...Jim Thompson

What I've done once in a situation where one level (idle, while not pulsing) had to be very precise was servo the logic supply for the drive chip. It think it was 74AC back then. A blanker acted like the TV black level clamp and then a regular opamp controlled a pass transistor until that clamp level was where I wanted it.

So if you had a "blind" level shifter of some sort behind the chip this would take care of any drift in the drive chip, the 3.3V rail voltage as well as the level shifter.

negative logic voltages. Gives reasonable speed with crap transistors. Not too precise. I don't know if it can be adapted to your use. Proper output voltages require setting the resistors properly.

Hmmm, transistors. I'd sort of forgot about those.

This almost works:

negative logic voltages. Gives reasonable speed with crap transistors. Not too precise. I don't know if it can be adapted to your use. Proper output voltages require setting the resistors properly.

But you get no DC precision to write home about. It'll drift all over the place when a cold front barrels through.

negative logic voltages. Gives reasonable speed with crap transistors. Not too precise. I don't know if it can be adapted to your use. Proper output voltages require setting the resistors properly.

Well, the ECL gate has an emitter follower output, so it's gross Vbe change with ambient temperature cancels the Vbe change of the PNP.

I *said* that it *almost* works.

negative logic voltages. Gives reasonable speed with crap transistors. Not too precise. I don't know if it can be adapted to your use. Proper output voltages require setting the resistors properly.

But it's "Larkin precise" ;-)

I posted a precise method at...

Newsgroups: sci.electronics.design Subject: Re: level shifter Date: Thu, 08 Mar 2012 15:15:13 -0700 Message-ID:

which absorbs wherever the Q/Qbar "queue" up and centers (adjustable) the drive point about Larkin's -0.7V to +0.1V desired range. But since it was me that posted that, there has been zero comment.

(Now the s*it will start :) ...Jim Thompson

negative logic voltages. Gives reasonable speed with crap transistors. Not too precise. I don't know if it can be adapted to your use. Proper output voltages require setting the resistors properly.

Did you try a hot RF transistor for low capacitance? These are nice:

Then couple it thermally to the EP51. Both ON and Micrel make those in a version with a thermal pad which doesn't have to be electrically connected. Really cool would be an RF PNP array like the HFA3135 or a bigger array where a 2nd PNP could run DC at same current against -0.7V. Then you could connect this thermal pad to the collector and it should track much better. I think the rule is that if you connect the pad it must be to the most negative voltage.

Circuit fine just wondering where you learned to draw the circuit upside down?

My training put the feedback components on top of the op amp and the "-" goes above the "+" on the opamp.

Took me a minute to flip it all in my head then it all made sense to me. Is this the now standard of drawing? After all I was trained starting in 1966.

Thanks

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Ha, this reminds me when I was a kid learning. I would look at circuits that were (-) on the common side, got used to all that use as the (+) being on the high side then, I start seeing lots of circuits based on having (+) as the common and everything in my head was backwards due to the use of many PNP's instead of NPN's

It's one of those learning processes where you can't allow yourself to adopt to a fixed way of lay outs. You must be able to think with out a road map.

jamie