PLL tricks

uoted...

If you use a product detector, it isn't quite as statistical, and you can s ensibly detect at 10MHz, even with franctional-N approximation to 10MHz.

A DDS approximation to 10MHz would be a whole lot closer, and the systemati c deviations you'd have to average out even smaller.

Provided that there enough samples - and the error being averaged is small enough - for the random noise to average to less than a picosecond in your

From this point of view, a bang-bang detector is not a good idea. The rando m signal you are averaging is either 1 or 0, which is to say either + or -5

With a fractional-N divider and a product detector you would get non-random offsets up to 6.4nsec but they can be guaranteed to average to zero over a ny 12.5usec interval, which is a lot less than 2msec

Only in a bang-bang detector.

Something like that. We'll probably lay out a nice multilayer proto board with a few candidate VCXO locations, 10 MHz filters, and dipswitches and trimpots in the loop lowpass filter to make it easy to tune. Seed that with SMA connectors for analysis, and experiment. Good intern sort of project.

Putting a cover over the XO, to keep air currents off it, can reduce jitter a lot.

This is cool:

It was done by one of the s.e.d. guys some time ago; Jeroen? It lets you convert a phase noise curve to RMS jitter.

I assume that a 1PPS pulse will happen exactly every 1e7 of the 10 MHz sine wave. If that's not true, we're in for interesting times.

The manual for the GPS box doesn't mention the phase relationship between the 10M and the 1PPS; I'll have to measure that and provide an FPGA tweak, just in case. I need to resync the 1PPS to the 10 MHz, and then promote that event up to 155.52 MHz, absolutely unambiguously.

They may not spec the phase of the 1 pps relative to the 10 MHz, but they should give you a jitter spec on the 1 pps. What is that number? That should give you enough insight.

That isn't the question. He is looking to make a PD with 1 ps jitter. He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of RMA jitter. How does the filter change this spec?

I'm only responding to your earlier statement that you wanted a PD with

The PD jitter doesn't matter. The oscillator jitter does.

It smooths out the statistical noise of the bang-bang flop, before it's applied to the VCXO input.

I'm surprised that I have to explain stuff this simple.

I want ballpark 1 ps time stability, and a bang-bang ECL phase detector is a simple way to get close to that. The PD jitter will get attenuated by the loop filter, so the VCXO jitter can be way less than the jitter of the PD flops, or the likely bigger jitter of the 10 MHz reference.

As noted, the stability and jitter that matters is at the output of the VCXO.

If your PD jitter doesn't matter why do you use the ECL FFs? It could all be done in the FPGA.

So why use ECL FFs?

It doesn't have to be.

Not that I am in anyway indicating what I am currently working on, I entered the thread to make a general discussion point that generating a high frequency VCO using LC tank multiplication will most likely to certain, result in much lower phase noise than using a PLL to lock/ that higher frequency with a HF (low Q) oscillator. i.e. Its difficult to get a high performance, high stability oscillator directly at say, 2.5 Ghz. Xtals are s*it up there. This may or my not have relevance to your particular problem. For example, a 50G/s optical system could take the HF VCO clock and lock it to incoming data.

So, for example, a 10MHz xtal VCO fed into tanks to multiple up, looks like a N*F VCO. This combined HF VCO could be locked in a PLL with your incoming

I would guess that your incoming 10 MHz has a low frequency (< 1Hz) phase noise way below that which a standard xtal oscillator has. Otherwise, I still wont understand why 10 mili Hz noise bothers you. Noise ramps up at

Kevin Aylward

An FPGA would have a horrible tempco, ballpark 10s of PS per degree C. And it would add massive jitter, from crosstalk and tiny Vcc wiggles and tiny temperature variations. Differential ECL is way less sensitive to things like that.

I make digital delay generators with an FPGA in a similar phase-locked loop. Uncompensated delay tempco is typically around 40 ps/degC and jitter is maybe 30 ps RMS. An ECL bangbang loop can be a couple ps RMS jitter and roughly 1 ps per degree C.

The FPGA could probably be improved, with a lot of work battling the P&R tools, but it won't approach the ECL.

None of which overcomes the basic fact that the GCD of 10MHz and

Measure the tempco of the inductors, add a tweak for PCB pad capacitance, Spice it.

Than add NTC caps (if you can buy the values that you need) or a DAC and a varicap. Or tweal the delay somewhere else in the system.

There may be a bandpass topology that has a parabolic or some such flat delay TC over some temperature region. But the inductors will be the killers. At 10 MHz, active filters are possible.

Saying "exactly" for timing coincidence which involves continuous waveforms is a trifle risky... :-)

The Motorola Oncore receivers (quite popular some years ago) exhibited this behavior. There's a predictable deterministic "sawtooth" pattern to the timing offset between "true start of second" and "leading edge of the PPS pulse". As noted, you can determine this offset after-the-fact for any particular pulse, and can even predict it fairly well some time in advance.

I believe that this situation remains true for many more-modern GPS receivers... the PPS pulse is synchronous to an internal clock (which is probably faster than that of the Oncore).

I'd guess that some high-end timing-grade GPS receivers may "bend" their internal clocks to reduce the clock-related PPS jitter... but there's always going to be some.

The question is whether the 1 PPS ever happens any more or any less than 10,000,000 cycles of the 10 MHz output.

I'd be shocked if it ever did.

The phase relationship between the 1PPS TTL rise, and the 10 MHz sine wave, can be measured and allowed for, as long as it never slips a full 100 ns.

Ok, so your ECL FFs are pointless? You just said the loop averages out the jitter...

So your binary counter chips are divide-by-(16 +- epsilon) ?

Cheers

Phil Hobbs

You're not thinking very hard, or have forgotten how to go from time to frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

Cheers

Phil Hobbs

Bill, you keep ignoring the problem of drift. It's quite true that you can get good noise performance with an ordinary phase detector, but if you estimate the drift level you need in order to maintain 1 ps accuracy, it's horrendously small.

According to John's measurements, the picosecond ECL DFF has jitter too small to measure easily and very low tempco of propagation delay. It also has some gigantic gain, so drift of other elements in the loop hardly contributes at all.

Cheers

Phil Hobbs