tolerances,
D-S dacs work just fine in FPGAs. They're especially handy for slow trims, like dc offset, vcxo freq, stuff like that. One FPGA pin and one external RC makes a pretty good dac.
John
added jitter on FPGAs
Nov 26, 2008
26 Replies
I've used external CMOS buffers to give a noise-free Voh for this application. FPGA outputs can have quite a lot of noise on them, coupled from other outputs on the same bank. (The numbers vary from family to family, etc.)
Regards, Allan
A delta-sigma dac needs a ton of lowpass filtering anyhow, so the only noise that matters is slow stuff on the +3.3 rail, which is usually easy to control. Most fpga's bank Vcc_out anyhow, so only the "dac bank" supply needs to be quiet at low frequencies.
John
:
s,
ohe
osts
aave
lta
eled
I have found that digital noise on an analog component can be a very
*real* problem. It is surprising where noise can come from. A component I was using turned out to have 0 dB of PSRR. It wasn't in the data sheet and I didn't think to ask. I only found out because there was a problem with buzzing in the output at certain times. When all the troubleshooting was done, the source turned out to be power supply noise. When the DSP was in the code to pass data to the output, it was in a loop at 300 Hz and the difference in power consumption between the wait loop and the "move data" loop was creating 10 mV of 300 Hz noise on the power rail. I suppose that would not be an issue if I wasn't using a crappy part. Still, with a VCO you need to be very careful about having a clean power supply. It doesn't take much to put noise of all frequencies on the rails and once there, it is hard to clean up... although I did find that a 1000 uF capacitor can do wonders at 300 Hz.Rick
Nice. What PFD frequency was the FPGA running at?
And certainly cheaper than purchasing a separate PLL IC if you already need an FPGA.
---Joel
Most recent case, we're locking a 128 MHz VCXO to an external 10 MHz reference, so we divided both down to 2 MHz. This phase detector gave us a lot less phase noise and phase error than any of the classic charge-pumps we tried to fake.
Given that there's some overlap designed into the up/down blips, the loop gain is higher (2x) in the overlap region than farther from zero phase error.
John
tolerances,
I'm looking to replace a 16bit (24bit but don't believe the specs) audio codec.
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required