Re: Designing the right clock tree for a multi-FPGA setup

Bob,

Good point: depending on his requirements, he may have to BOTH send a high quality, low jitter clock to all FPGAs, AND forward clocks from each FPGA to other ones for source synchronous transfer operation on his communications between devices.

Austin

Okay, let's be more precise: The clock frequencies I'd like to distribute are in the range of 180 - 300 MHz, i.e. it is a challenging task. The signal busses between the FPGAs should carry signals in that range, too. Data is exchanged synchronously, so there is not much room for synchronization I think...!?

Gero

Hi Geronimo, This alternative will work. You should use a clock buffer to duplicate your clock three times.. The amount of jitter is generates will be at least an order of magnitude less than the jitter introduced just getting on to the FPGAs' internal clock trees.

You might also consider source synchronous busses to get data between FPGAs in addition to the star topology.

I see no advantages in using this third method.

It's hard to advise you without a specific set of requirements, but I'd say your design stands a good chance of success simply because you're thinking hard about this up front! :-) HTH., Syms.

Gero,

OK, then I am correct, you not only need a good system synchronous clock to each FPGA, but you also must use clock forwarding to send/receive data between devices.

Aust> Okay, let's be more precise: The clock frequencies I'd like to distribute

"Symon" schrieb im Newsbeitrag news:f7805h$1sk$ snipped-for-privacy@aioe.org...

Sounds interesting. What do you mean by that? Could you please go a little bit more into details? I heard about "source synchronous busses" a while ago but unfortunately I don't know what it is... sorry!

Thanks.

Gero

Hi Gero, The source of the data provides a clock along with the data. You should be able to find stuff on the FPGA manufacturers websites to help you along... HTH, Syms.

"austin" schrieb im Newsbeitrag news:f78203$ snipped-for-privacy@cnn.xilinx.com...

I'm sorry, Austin! I am not so familiar with the topic. What do you mean by "system synchronous clock"? Isn't that just the description for "identical clock to every FPGA" or am I wrong? And how should clock forwarding be done? If the data arrives at every FPGA with its own clock, but the FPGA is clocked by another skewed (or even jittered) clock, how can synchronization be achieved, anyway? I appreciate your comment. Thanks in advance.

Gero

Wikipedia has a good article :

Basically when A sends stuff to B :

- A and B can be clocked by the same global clock (the good old way, with clock skew etc) - B can generate a clock and send it to A (then you get problems if traces are long) - A can generate a clock and send it to B

Last case means, A (source) can send a clock that is perfectly synchronized with the sent data. Hence, if clock and data go through the same trace length, B receives well synchronized clock and data, so B's flip flops are happy. Of course, A's clock will not have the same phase as B's internal clock, so B needs some way of putting them back in phase (FIFO, etc).

One could argue that stuff like SATA or Ethernet are source synchronous, too, even though there is no separate clock, as it is embedded in the data. It would not be possible for the controller to clock the harddisk when the frequency is so high that the length of the cable contains several different bits propagating along the transmission line !

Gero,

As noted by others, you need a high quality clock to each FPGA. They do not need to be phase matched, or equal length. Just a good very low jitter clock to each one from a clock distribution device (like the ICT quad LVDS clock buffer + cleanup PLL -- a good choice I use -- I think it is a 8745?):

or equivalent. The nice thing about some of these parts is that you may use a lower frequency less expensive oscillator, and this part will multiply the frequency, and remove jitter, too (as opposed to buying a much more expensive higher frequency oscillator).

This then is the basis for all timing in each FPGA.

To get from one FPGA to another, or from one FPGA to an ASIC/ASSP:

You would use a source-synchronous interface. This one where you send the data, and a clock from one, to the other. Since the data jitter will be exaclty what the clock jitter is (they came through the same paths, close to each other), system jitter, and clock jitter are almost able to be ignored. The receive side uses the forwarded clock to register the incoming data. Often the DCM is used to phase shift the sample point to exactly the center of the "eye" so you have best timing margin. The data paths with clocks must all be delay matched (all signals must leave and arrive in sync with each other). We have tables of the delay from the silicon, to the pad, and you need to have your pcb designer take this into account.

There is also a source synchronous IO block built into V4, and you can do things like use one forwarded clock to frame 4 bits on each wire (the forwarded clock is running at 1/4 the system clock). The SSIO block takes care of the serialization and parallel conversion of each IO.

Chapter 8.

Also look at the SPI POS 4.2 IP core, and how it is specified for inter chip communications (this is an industry standard for wide, fast, DDR buses).

So, in review: system synchronous (one clock to all chips) for each chip to use for all of its internals, and generating forwarded clocks; AND source synchronous (a forwarded clock) for each data bus between devices.

Searching on "source synchronous" and "spi pos 4.2" and reading the user's guides on the SSIO blocks will get you up to speed.

Austin

Austin, thank you very much for your detailed answer!

It became quite clear for me now. Just one more question: How do I practically generate the forwarded clocks? Just a toggling 1-bit signal (1..0..1..0..)? Do I have to use dedicated clock I/Os? I think so...!?

Regards, Gero