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[XILINX][V2PRO]IOB tristate pins.

So, the IOB in V2PRO has two tristate pins, T1 and T2. As far as I can tell, they're interchangeable in standard, i.e. non DDR, modes. In one of my designs it would help if I could get the tools to use T2 rather than the T1 it defaults too. There's slightly faster direct routing available to the T2 pin, saving 200ps from my timing budget. Sadly, the tools don't want to swap the T1 and T2 pins. Directed routing doesn't work; the route to T2 fails. I'm using ISE6.3. (waiting for SP3 before moving to ISE7.1!!) I'm not using any of the FFs in the IOB. Questions.

1) Is it true that the T1 and T2 pins are interchangeable in this mode? 2) How can I get the tools to swap the pins? 3) Is there an IOB instantiation component that includes the T2 pin? Any thoughts gratefully received. TIA, Syms.
Reply to
Symon
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Symon, I sent you a lengthy private response. If you want to share some of it, be my guest... Peter Alfke

Reply to
Peter Alfke

Peter, Much appreciated! For the record, I found the pertinent part of the response is :-

Since the designer is not registering the output, there is no way to force the tool to use the T2 pin. If the designer was using the register then it would be possible to use one of the following BEL constraints to force the tools to use the T2. There is not BEL for the Asynch path so there is no way to constrain it. I do believe though, that the designer feels that the T2 pin is faster because of the location of the source. I believe if the designer were to change the placement of the source then he could get the faster path for the T1 pin.

I did find a better placement for one instance of my design; only two instances left to analyse! The differences between the instances are because of the different combinations of IOBs used within the sets of four IOBs in each row in the FPGA array. Probably! Thanks again, Syms.

Reply to
Symon

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